This paper presents preliminary results regarding system-level power awareness for FPGA implementations in wireless sensor networks. Re-configurability of field programmable gate arrays (FPGA) allows for significant flexibility in its applications to embedded systems. However, high power consumption in FPGA becomes a significant factor in design considerations. We present several ideas and thei...

Pseudorandom number generation (PRNG) is a key element in hardware security platforms like fieldprogrammable gate array FPGA circuits. In this article, 18 PRNGs belonging in 4 families (xorshift, LFSR, TGFSR, and LCG) are physically implemented in a FPGA and compared in terms of area, throughput, and statistical tests. Two flows of conception are used for Register Transfer Level (RTL) and High-...

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routin...

For many years, research on FPGA-type programmable hardware architectures has focused mainly on optimising regular non-hierarchical architectures. In the exploration of their design space, some design parameters have a significant impact on the layout area, which is directly related to interconnect delay. An estimation of this impact can be derived from a prediction of the area of the basic FPG...

This paper proposes a new high-level approach for optimising field programmable gate array (FPGA) designs. FPGA designs are commonly implemented in low-level hardware description languages (HDLs), which lack the abstractions necessary for identifying opportunities for significant performance improvements. Using a computer vision case study, we show that modelling computation with dataflow abstr...

The paper focuses on the use of field programmable gate arrays (FPGA) for signal processing applications. By allowing designers to create circuit architectures developed for the specific applications, high levels of performance can be achieved using FPGA for many digital signal processing (DSP) applications providing considerable improvements over conventional microprocessor and dedicated DSP p...

Currently, the Computer-Aided Engineering (CAE) environments for designing Field-Programmable Gate Arrays (FPGAs) do not support the simulation of FPGA reprogrammability, hence prototyping of adaptive systems relies upon using the actual FPGAs. The FPGA architecture baselined in this paper, similar to a commercially-available FPGA architecture, supports partial reconnguration without disturbing...

In this paper we present a self con gurable multiplication technique allowing vari able con guration time for a class of LUT based Field Programmable Gate Arrays FPGAs which exist today We show this technique to be implementable on FPGA architectures allowing internally addressable RAM primitives to be directly mapped to the Logic Elements LEs of the logic resource This provides run time read w...

The role of Chip Implementation Center (CIC), founded in 1992 under the National Science Council (NSC) of Taiwan R.O.C., is to provide the services for the fabrication of multi-project chip (MPC), the procurement/integration of software CAD tools, and the promotion of IC and FPGA design/testing/CAD software technology for academia in Taiwan. To date, CIC assisted 86 universities and polytechnic...

In this paper, we present a novel temporal partitioning methodology for dynamically reconfigurable computing systems to reduce the communication costs of the design. This aim can be reached by minimizing the transfer of data required between design partitions. Our algorithm use the network flow-based multi-way task partitioning algorithm to minimize communication costs for temporal partitioning...