Sub-threshold is a new paradigm in the digital VLSI design today. In Sub-threshold region, transistors are operated in sub-threshold voltage. This paper examine the Carry Look Ahead (CLA) Adder with dual mode logic (DML)principle, in which gates are operated in sub-threshold regime and comparison of results with Conventional basic Carry look ahead adder . The number of gates in CLA is 5 includi...

The aim of this paper is to study the threshold behavior for the satisfiability property of a random k-XOR-CNF formula or equivalently for the consistency of a random Boolean linear system with k variables per equation. For k ≥ 3 we show the existence of a sharp threshold for the satisfiability of a random k-XOR-CNF formula, whereas there are smooth thresholds for k = 1 and k = 2. Mathematics S...

The discrepancy method is widely used to find lower bounds for communication complexity of XOR games. It is well known that these bounds can be far from optimal. In this context Disjointness is usually mentioned as a case where the method fails to give good bounds, because the increment of the value of the game is linear (rather than exponential) in the number of communicated bits. We show in t...

We propose to design multispin quantum gates in which the input and output two-state systems (spins) are not necessarily identical. We describe the motivations for such studies and then derive an explicit general two-spin interaction Hamiltonian which accomplishes the quantum XOR gate function for a system of three spins: two input and one output. PACS numbers: 03.65.Bz, 85.30.St – 1 –

As unconventional computation matures and non-standard programming frameworks are demonstrated, the need for formal verification will become more prevalent. This is so because “programming” in unconventional substrates is difficult. In this paper we show how conventional verification tools can be used to verify unconventional programs implementing a logical XOR gate.

We propose to design multispin quantum gates in which the input and output two-state systems (spins) are not necessarily identical. We describe the motivations for such studies and then derive an explicit general two-spin interaction Hamiltonian which accomplishes the quantum XOR gate function for a system of three spins: two input and one output.

In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using different modules. The Various modules are AND gate OR with six transistors, While XOR is both eight transistors transistors. transistor module gives optimized results. Another one four multiplexer implemented Pass logic (PTL) style. full adder 18 through PTL Here because of style number count such that c...

This paper presents an area-time-efficient systolic structure for multiplication over GF(2 m ) based on irreducible all-one polynomial (AOP). A novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay is used. Also the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input ...

We point out and simulate the possible utility of anti-coherence in molecular electronics. In ballistic transfer through a molecule with a large loop that fulfils a certain phase condition on the loop structure, the transfer would be anticoherent. By applying one or two control voltages to the molecule, that modify the relative phase through the two parts of the loop, the transfer could be cont...

Polymorphic digital circuits are circuits composed of polymorphic (multifunctional) as well as ordinary gates. In addition to its standard logic function (such as NAND), a polymorphic gate exhibits another logic function which is activated under a specific condition, for example, when Vdd, temperature, illumination or a special signal reaches a certain level. This paper describes existing polym...