A recent publication introduced a Visual Crypto (VC) system, based on the polarisation of light. This VC system has good resolution, contrast and colour properties. Mathematically, the VC system is described by the XOR operation (modulo two addition). In this paper we investigate Threshold Visual Secret Sharing schemes associated to XOR-based VC systems. Firstly, we show that n out of n schemes...

This paper presents two methods for encryption and decryption of images using XOR operation. In the first method the original image is encrypted by the key image using XOR operation and decryption process also uses the same key image with XOR operation. In the second method one of the bit planes of the key image is used for encrypting the bit planes of the original image and shuffling is done f...

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been inve...

Non-local games are widely studied as a model to investigate the properties of quantum mechanics as opposed to classical mechanics. In this paper, we consider a subset of non-local games: symmetric XOR games of n players with 0-1 valued questions. For this class of games, each player receives an input bit and responds with an output bit without communicating to the other players. The winning co...

OMBINING entered variable (EV) subfunctions and C XOR patterns in a Karnaugh map (K-map) extraction process [3] is a special and powerful form of K-map multilevel function minimization. Used with two-level logic forms (AND and OR functions) this multilevel minimization approach leads to XOIUSOP, EQVPOS and hybrid forms that often represent a substantial reduction in the hardware not possible ot...

In this paper, a new design of three transistor XOR gate is proposed using Independent Driven Double Gate MOSFET to achieve ultra-low power in sub threshold conduction. The proposed design has been compared with the three transistor XOR implemented using Symmetrical Driven Double Gate MOSFET in sub threshold region. A three transistor XOR gate designed using Independent Driven Double Gate MOSFE...

Recent research on Boolean satisfiability (SAT) reveals modern solvers’ inability to handle formulae in the abundance of parity (xor) constraints. Although xor-handling in SAT solving has attracted much attention, challenges remain to completely deduce xor-inferred implications and conflicts, to effectively reduce expensive overhead, and to directly generate compact interpolants. This paper int...

A hybrid network is proposed in dynamic CMOS XOR/XNOR gate to avoid signal skew and reduce the power consumption. Compared to the standard N type dynamic gate leakage power, dynamic power and layout area of the novel XOR/XNOR gate are reduced. In this paper we studied different technologies, their merits and demerits. Comparison of different technologies is completely on the basis of leakage po...