New semiconductor wafer fabrication facilities use Front Opening Unified Pods (FOUPs) as a common unit of wafer transfer. Since the number of pods is limited due to high costs, and the increase in wafer size to 300-mm reduces the number of wafers required for a customer order, combining multiple orders into a single job is a necessity for efficient production. We investigate the multiple orders...

 In through-wafer silicon etching using highdensity low-pressure inductively coupled plasma, a notching (or footing) effect occurs at the silicon-insulator interface. The insulator layer is common, as the silicon wafer has either an oxide layer to avoid break through of the plasma or is bonded to a handle wafer using either photoresist or other adhesives. Notching at the foot of micro-structur...

This paper explores the feasibility of integrating in-situ sensors onto the surface of a silicon wafer, with the objective of placing this wafer into a processing tool to obtain real time measurements. This technique has numerous benefits: increased measurement speed, reduced sensor introduction cost, and increased spatial and temporal information. Various sensors and sensor wafers have been de...

As part of a larger effort aimed at providing symbolic, computer-aided tools for semiconductor fabrication experts, we have developed qualitative models of the operations performed during semiconductor manufacture. By qualitatively simulating a sequence of these modele we generate a description of how a wafer is affected by the operations. This description encodes the entire history of processi...

1.1.3 Chemical and physical properties of the pure substance (a) Description: Grey, cubic crystals (Lide, 2003) (b) Melting-point: 1238 °C (Lide, 2003) (c) Density: 5.3176 g/cm (Lide, 2003) (d) Solubility: Insoluble in water (Wafer Technology Ltd, 1997); slightly soluble in 0.1 M phosphate buffer at pH 7.4 (Webb et al., 1984) (e) Stability: Decomposes with evolution of arsenic vapour at tempera...

In this paper, we present and analyze yield enhancement designs for wafer scale Cube Connected Cycles (CCC). Improvements in yield can be achieved through silicon area reduction and/or through the incorporation of defect/fault tolerance into the architecture. Consequently, we first propose a new compact layout strategy for CCC. We then present a novel implementation of wafer scale CCC based on ...

Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in-situ approach for estimating wafer warpage profile during the thermal processing steps in microlithography process. A programmable multizone thermal processing system is developed to demonstrate the ap...

A 1.02nW current reference is designed with only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation. Thirty-two measured chips from 5 corner wafers in 180nm CMOS technology show an untrimmed within-wafer spread (σ/μ) of 1.6% and across-corner wafer-to-wafer spread of ±4.7%. The measured average temperature coefficient is 282ppm/°C from −40°C to...

In this work we present a numerical, multi-scale approach to estimate the strength of a wafer-to-wafer metallic thermo-compression bonding. Following a top-down approach, the mechanical problem is handled at three different length scales. Taking into account control variables such as temperature, overall applied force over the wafer and contact surface roughness, it is shown that the proposed a...