The CD4046BC micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the sign...

This study proposes using wireless low power thermal sensors for basal-body-temperature detection using frequency modulated telemetry devices. A long-term monitoring sensor requires low-power circuits including a sampling circuit and oscillator. Moreover, temperature compensated technologies are necessary because the modulated frequency might have additional frequency deviations caused by the v...

V m f 4 AbstractA phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. . Implemented in 1 .w CMOS, the PLL has a 111-29OMHz range, phase noise of -92.3dBdHz at a 5OkHz offs...

This paper describes the factors that limit the tuning range of monolithic LC voltage-controlled oscillators (VCOs), especially at low supply voltages, and introduces circuit techniques that alleviate this problem. Incorporating such techniques, a 1.8GHz CMOS oscillator achieves a tuning range of 120MHz with a relatively constant gain while exhibiting a phase noise of -100dBc/Hz at 500kHz offse...

In this paper, a programmable phase-locked-loop (PLL)-based fractional-N frequency synthesizer, with the capacity of automatically adjusting the nominal frequency of voltage-controlled oscillator (VCO) is presented. The monolithic wideband VCO, with digital and analog control, is capable of operating from 1.6GHz to 2.5GHz. Analog control voltage is only varied from 0.8V to 1.2 V to improve the ...

A dual-band monolithic voltage-controlled oscillator (VCO) has been fabricated by using the 0.18 lm 1P6M CMOS technologies. The switching transistors concept used in the tank circuit realizes the dual-band VCO operation. In order to reduce the phase noise, the pMOS transistors were used in the VCO design. The dual-band VCO demonstrates the phase noise (100 kHz offset) of )98 dBc/Hz at 2.6 GHz a...

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in rang...

A prototype dual-mode voltage-controlled oscillator supporting two simultaneous oscillation modes is fabricated and demonstrated in a 0.18 mm CMOS process. The oscillator has two resonant ports while sharing one bias. Injection locking is applied to lock the low frequency, 4.8 GHz, to half of the high frequency, 9.6 GHz. The oscillator core consumes 7 mA from a 1.8 V supply. Measurement shows a...

A fifth-order CMOS continuous-time Bessel filter with a tunable 6to IS-MHZ cutoff frequency is described. This fully balanced transconductance-capacitor (G~ – C) leapfrog filter achieves a dynamic range of 55 dB while dissipating 96 mW in a 5-V 0.9-pm CMOS process. The on-chip master–slave tuning system uses a voltage-controlled oscillator (VCO).

Process and temperature variations have become a serious concern for ultra-low voltage (ULV) technology. The clock generator is the essential component for the ULV very-large-scale integration (VLSI). MOSFETs that are operated in the sub-threshold region are widely applied for ULV technology. However, MOSFETs at subthreshold region have relatively high variations with process and temperature. I...