Implementation constraints on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Turbo codes and low-density parity check codes, in particular, are evaluated in terms of ...

The class of median filters has been extended to include weighted order statistics (WOS) filters, to improve the flexibility of the filtering operation. The WOS filter weights each input within a sample window, and thus retains the original temporal order information. In this paper, we present efficient VLSI architectures for nonrecursive and recursive WOS filters based on (i) array (ii) stack ...

Neuromorphic electronic engineering takes inspiration from the biological organization of nervous systems to rethink technology computing, sensing, and actuating (see “Summary”). It started three decades ago with realization by Carver Mead, a pioneer very large-scale integration (VLSI) technology, that operation conventional transistor in analog regime closely resembles biophysical neuron <xref...

The styles of computation used by biological systems are fundamentally different from those used by conventional computers: biological neural networks process information using energyefficient, highly parallel, event-driven architectures as opposed to clocked serial processing. They are composed ofmultiple instances of heterogeneous elements and are able to self-repair, adapt and learn from the...

This paper presents a low-latency hardware accelerator for modular polynomial multiplication lattice-based post-quantum cryptography and homomorphic encryption applications. The proposed novel multiplier exploits the fast finite impulse response (FIR) filter architecture to reduce computational complexity of schoolbook multiplication. We also extend this structure $M$-parallel architectures whi...

The program environment for automatic designing of the application specific parallel architectures (liked to VLSI processor arrays) is proposed. The environment consists of three compatible programs which allow to construct and to visualize the dependence graph of algorithms given by nested loops, and then mapping of these algorithms onto corresponding processor array architectures with desired...

In this chapter, we address the performance advantage of using optoelectronic areaI/O to realize three-dimensional multi-FPGA architectures. The performance of such architectures strongly depends on the latency of the optoelectronic components used. Determining the optical link latency that is required to benefit from the promised advantage is far from trivial. We present first estimates of the...

Processing an image in the RGB color space, with a set of RGB values for each pixel is not the most efficient method. To speed up some processing steps many video compression and communication techniques use luminance/chrominance color spaces, such as YCrCb, making a mechanism for converting between formats necessary. Therefore, techniques which efficiently implement this conversion are desired...

Configurable computing has recently gained much attention with the promise of delivering an order of magnitude performance improvement over general purpose processors. In this paper we contrast the abstract models of reconfigurable architectures and actual hardware available for configurable computing systems. There is a wealth of ideas related to abstract models of reconfigurable architectures...