This paper presents a logic-based structural hardware design environment, called HIDE, developed at the Queen’s University of Belfast. Central to this environment is a hardware description language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog. The guiding principle in desig...

This study describes a hardware modeling environment of built-in-self-test (BIST) for System on Chip (SOC) testing to ease the description, verification, simulation and hardware realization on Altera FLEX10K FPGA device. The very high speed hardware description language (VHDL) model defines a main block, which describe the BIST for SOC through a behavioral and structural description. The three ...

This paper provides an overview of the VHDL AMS hardware description language for analog and mixedsignal applications like the switched mode power supply which is designed by describing the major elements or components of the system with the help of this hardware descriptive language and illustrating it using Hamster which is a simulation software for VHDL and Verilog Descriptive Language. Inde...

Various languages have been proposed to describe synchronous hardware at an abstract, yet synthesisable level. We propose a uniform framework within which such languages can be developed, and combined together for simulation, synthesis, and verification. We do this by embedding the languages in Lava — a hardware description language (HDL), itself embedded in the functional programming language ...

The ever increasingly number of transistors possible in VLSI circuits compounds the diiculty in ensuring correct designs. Formal veriication has been touted as a means of overcoming this problem, but most of the work in this area has been directed at standalone theorem provers. Before veriication is accepted by the VLSI design community, the stand alone veriication tools that are in use in the ...

This paper provides an overview of the VHDLAMS hardware description language for analog and mixedsignal applications like the phase locked loop system which is designed by describing the major elements or components of the system with the help of this hardware descriptive language and illustrating it using Hamster which is a simulation software for VHDL and Verilog Descriptive Language. Index T...

In previous work we have demonstrated how the functional language SAFL can be used as a behavioural hardware description language. Other work (such as μFP and Lava) has demonstrated that functional languages are apposite for structural hardware description. One of the strengths of systems such as VHDL and Verilog is their ability to mix structuraland behavioural-level primitives in a single spe...

This paper reports on some initial results in using LOTOS as a hardware description language. LOTOS, the Language Of Temporal Ordering Specifications, is a language that has been conceived in the framework of Open Systems Interconnection (OSI) standardization as a tool for the formal description of OSI services and protocols. We present some examples to show how LOTOS can be applied to the spec...

This contribution reports on an approach to hardware/software codesign based on a state transition system design language MAD. MAD has been used for software design for some time, but is now being extended to hardware design by adding the hardware description language VHDL as one of its target languages. The experience of adding a new dimension (i.e. hardware) to the design space and of dealing...