The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that can significantly reduce this overhead. By using runlength and other compression techniques, files can be compressed by a factor of 3.6 times. Bus transfer mechanisms and decompression hardware are also discussed. Thi...

Molecular Dynamics simulations have become an interesting target for acceleration using Field-Programmable Gate Arrays (FPGA). Still to be attempted completely in FPGA hardware is the computation of the Coulombic interactions using the Smooth Particle Mesh Ewald (SPME) algorithm. In this work, we describe the design, the implementation, and the verification effort of an FPGA compute engine, nam...

In this Paper an efficient method of FPGA based design and implementation of area efficient Sobel Edge detection filter is presented using a combination of hardware and software components. The FPGA provides the necessary hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipelined method is used to implement the edge detection filter. This ap...

The MAC unit is considered as one of the fundamental operations in DSP and it becomes a basic component in ApplicationSpecific-Integrated-Circuits (ASIC).The MAC unit determines the speed of the overall system; it always lies in the critical path. Developing a high speed MAC is crucial for real time DSP applications. In other words the MAC operation is the main computational kernel in Digital S...

A power efficient Fast Fourier Transform (FFT) processor for use in the Direction of Arrival (DOA) estimation of a wideband waveform is presented. The target device for implementation is a Xilinx Spartan-3 Xc3s200 Field Programmable Gate Array (FPGA). The FFT processor was developed using the Xilinx ISE in Verilog code. Although the parallel and pipelined architecture uses a large portion of th...

It is well known that Field Programmable Gate Arrays (FPGAs) can be used to accelerate calculations that take too much time on a Central Processing Unit (CPU). Methodologies have been proposed to reconfigure the FPGA at run time, depending on the needs of the system. The CPU and FPGA generally communicate through message passing, letting the programmer decide exactly which data needs to be pass...

Embedded systems design often involves writing code in high-level languages such as C/C++ and Java and optimizing using Assembly while minimizing design time. Equally important is the choice of the execution target. Among these microprocessor targets are microprocessor cores for FPGAs. These cores are useful for applications that also contain application-specific hardware implemented on the FPG...

Harp1 is a circuit board designed to exploit the rigorous compilation of parallel algorithms directly into hardware. It includes a transputer closely-coupled to a Field-Programmable Gate Array (FPGA). The whole system can be regarded as an instance of a process in the theory of Communicating Sequential Processes (CSP). The major elements themselves can also be viewed in the same way: both the t...

This paper presents an application of LabVIEW graphical programming and FPGA technology in the area of sensor calibration. A water quality sensor calibrator based on compact reconfi gurable FPGA core that works under a real-time controller is described. The system provides automatic calibration of stand alone sensors such as turbidity, pH or conductivity using diff erent calibration solutions t...

Using software OS, real-time operation is constrained by acquisition and preprocessing tasks of input signals. In this way, this paper presents an implementation of a real time target tracking behaviour, from snapped images of the environment, as an example of how to take advantage of real-time hardware devices as a helpful systems for control architectures. A specific board based on FPGA/DSP p...