This paper describes the design of a novel CMOS binary fulladder structure which incorporates four-valued signalling internally. A biased CMOS pseudo-lineaadder provides a quaternary signal representing the number of ones in the three binary inputs. Three area-ratioed CMOS inverters interpret this to provide three binary signals which, combined in conventional static CMOS logic, generate the su...

Moore's law describes a long-term trend in the history of computing hardware. The conventional methods have reached his limits so new fields has to be exploited. Such a concept is 3-Dimensional integration where the components are arranged in 3D plane. This arrangement can increase the package density of devices. The successful construction of 3D memory can lead to a new revolution in designing...

In this paper we consider the thermoelastic plate equation with localized thermal dissipation of memory type, proposed by Gurtin and Pipkin [3]. We will show that the solution of the corresponding model decays exponentially as time goes to infinity, provided the relaxation function decays exponentially. The mean difference with others thermoelastic system is that the whole system is of hyperbol...

We analyze energy consumption in optical modulators operated in depletion and intended for low-power interconnect applications. We include dynamic dissipation from charging modulator capacitance and net energy consumption from absorption and photocurrent, both in reverse and small forward bias. We show that dynamic dissipation can be independent of static bias, though only with specific kinds o...

The scaling of CMOS technology has progressed rapidly for three decades, but may soon come to an end because of powerdissipation constraints. The primary problem is static power dissipation, which is caused by leakage currents arising from quantum tunneling and thermal excitations. The details of these effects, along with other scaling issues, are discussed in the context of their dependence on...

This paper reports three design improvements for CMOS latches hardened against single event upset (SEU) based on three memory cells appeared in recent years. The improvement drastically reduces static power dissipation, reduces the number of transistors required in the VLSI, especially when they are used in the Gate Array. The original cells and the new improved latches are compared. It is show...

due to the high penetration of wind farms in the networks, they can have a significant role in the control of power systems. in this paper, wind farms (wfs) are used to improve the static security margins of the power system. generation rescheduling is one of the remedies to improve the static security margins of the power system. in this paper, the generation rescheduling is presented based on...

Domino logic circuits have faster operating speed than commonly used static logic ones, because they have lower input capacitances and no contention during transition. However, Domino logic circuits have more power dissipation than static logic ones, since their clock tress with high switch activity dissipates large energy. A low-power superthreshold computing scheme is proposed to reduce power...

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static dif...

As device sizes continue to shrink and circuit complexity continues to grow, power has become the limiting factor in today’s processor design. Since the power dissipation is a function of many variables with uncertainty, the most accurate representation of chip power or macro power is a statistical distribution subject to process and workload variation, instead of a single number for the averag...