In this study, a three-dimensional “atomistic” circuitdevice coupled simulation approach is advanced to investigate the process-variation and random dopant induced characteristic fluctuations in planar metal-oxidesemiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, ...

Industry demands Low-Power and HighPerformance devices now-a-days. Among the various embedded memory technologies, SRAM provides the highest performance along with low standby power consumption. In CMOS circuits, high leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation due to reduction in threshold voltage, channel length, and gate oxide thicknes...

Portable devices demand for low power dissipation. To reduce power dissipation, the subsystem in a device needs to be designed to operate at low power and also consume low power. Significant progress has been made in low power design of dynamic RAM’s. Static RAM’s are also critical in most VLSI based system on chip applications. Basic SRAM bit cell consists of 6T. Few designs using 4T are also ...

Memory is an important part of any electronic device. In today's world static random access memory (SRAM) is widely used as memory. The major issues for design of SRAM are power loss, delay and stability. This paper presents a modified form of a symmetric eight-transistor SRAM bit-cell. In this paper transmission gate has been used as access transistor which provides rail-to-rail swing. Moreove...

This paper presents a fast and low-power Static Random Access Memory (SRAM) design. SRAM are widely used in computer systems and many portable devices. Proposed SRAM is faster because of precharging at a desired voltage. For the most recent CMOS technologies leakage power dissipation has become a major concern. According to the International Technology Roadmap for Semiconductors (ITRS), leakage...

We present a side-channel attack based on remanence decay in volatile memory and show how it can be exploited effectively to launch a non-invasive cloning attack against SRAM PUFs — an important class of PUFs typically proposed as lightweight security primitive with low overhead by using the existing memory of the underlying device. We validate our approach against two SRAM PUF implementations ...

This paper is based on the observation of 8T single ended static random access memory (SRAM) and two techniques for reducing the sub threshold leakage current, power consumption are examined. In the first technique, effective supply voltage and ground node voltages are changed using a dynamic variable voltage level technique(VVL). In the second technique power supply is scaled down. This 8T SRA...

When working for low power application the main estimation is to reduce leakage components and parameters. This stanza explores a vast link towards low leakage power SRAM cells using new technology and devices. The RAM contains bi-stable cross coupled latch which has V_th higher in write mode access MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and lower V_th in read access mode MO...

In this work, the effect of displacement defect (DD) owing to cosmic rays on six-transistor (6T) static random access memory (SRAM) with a 3 nm node nanosheet field-effect transistor (NSFET) is investigated using technology computer-aided design (TCAD) simulation. order comprehensively study uncertainty radiation NSFET 6T SRAM, shape DD cluster cross-section and damaged by in SRAM are considere...

The most research on the power consumption of 6T SRAM has been focused on the static power dissipation and the power dissipated by the leakage current. On the other hand, as the current VLSI technology scaled down, the sub-threshold current increases which further increases the power consumption. In this paper we have proposed 6T (8 X 8) SRAM cells using MCML technology which will reduce the le...