نتایج جستجو برای: soi
تعداد نتایج: 4097 فیلتر نتایج به سال:
Magnetic transport of holes in Ge/Si core/shell nanowires (NWs) is investigated under the control of dual electrical gating. The strength of the spin–orbit interaction (SOI) is analyzed from the weak-antilocalization (WAL) of the magnetoconductance (MC) as a function of a perpendicular magnetic field. By superimposing a small alternating signal on the voltage offset of both gates the universal ...
Enhanced third harmonic (TH) generation from Silicon-On-Insulator (SOI) planar waveguides as well as SOI photonic crystal (PhC) slabs is studied in different angular configurations, both in the visible and infrared energy ranges. In the SOI planar waveguide, the multilayer structure causes the optical properties such as TH reflection to be different from those of bulk silicon samples. This beha...
As scaling down MOSFET devices degrade device performance in term of leakage current and short channel effects. To overcome the problem a newer device Silicon-on-Insulator (SOI) MOSFET has been introduced. The Fully Depleted (FD) SOI MOSFETs also suffer from short channel effects (SCE) in the sub 65 nm regime due to reduction in threshold voltage. Several investigations are going to reduce the ...
Purpose Total knee arthroplasty (TKA) is increasing in frequency and cost. Optimization of discharge location may reduce total expenditure while maximizing patient outcomes. Although preoperative illness rating systems-including the American Society for Anesthesiologists Physical Classification System (ASA), severity of illness scoring system (SOI), and Mallampati rating scale (MP)-are associat...
In this paper, a brief overview of TID effect in SOI technology is presented. The introduction of buried oxide(BOX) adds vulnerability to TID effect in SOI transistors because of its large thickness. Also the BOX introduces special charge traps, the delocalized spin centers, which in most cases are positive. The charge buildup in BOX could increase the leakage current in front gate transistor i...
Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.
For SOI nMOSFET, the impact of high tensile stress contact etch stop layer (CESL) on device performance and reliability was investigated. In this work, device driving capability can be enhanced with thicker CESL, larger LOD and narrower gate width. With electrical and body potential inspection, serious device’s degradation happened on SOI-MOSFET with narrow gate device because of STI-induced ed...
Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parame...
− This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pnjunction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and νMOS circuits. Index Terms −SOI, gated-pn junction, neural logic,
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