The main objective of the proposed work is implementing the 32 bit Vedic and Baugh-Wooley multiplication operation with Carry-Save methodology to reduce the average time and delay of operations. This system contain a high speed low power digital multiplier by using advantage of Vedic multiplication algorithms with a very efficient leakage control technique called multiple channel conventional m...

In this paper, a single precision IEEE 754 floatingpoint multiplier with high speed and low power is presented. The bottleneck of any single precision floating-point multiplier design is the 24x24 bit integer multiplier. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 24x24 bit multiplication operation is...

Palindromic representation is generally used to reduce space and time complexities in Gaussian normal basis (GNB) multiplier with even type t. However, palindromic representation is inapplicable for a GNB multiplier with odd type t (t ≥ 2). This study therefore develops a palindromic-like representation for a GNB multiplier with odd type t. The proposed systolic GNB multiplier with odd type t r...

Scheming multipliers that are of high-speed, low power, and standard in design are of substantial research interest. By reducing the generated partial products speed of the multiplier can be increased. Several attempts have been made to decrease the number of partial products generated in a multiplication process. One of the attempt is Wallace tree multiplier. This paper aims at designing and i...

Multiple Valued Logic (MVL) has some important benefits such as increased data density, increased computational ability, reduced dynamic power dissipation Therefore with the help of Multiple Valued Logic (MVL) we have designed two quaternary multiplier architecture. The partial products in the multiplier are designed with quaternary voltage mode circuits. Each multiplier architecture is designe...

An adiabatic logic is a technique to design low power digital VLSI’s. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2 μm CMOS process. The experimental results show that the multiplier was opera...

Comparing the performance of a set of activities or organizations under uncertainty environment has been performed by means of Fuzzy Data Envelopment Analysis (FDEA) since the traditional DEA models require accurate and precise performance data. As regards a method for dealing with uncertainty environment, many researchers have introduced DEA models in fuzzy environment. Some of these models ar...

This study introduces a reversible optical fulladder. Also optical NOT and NOR gates are implemented through Electro-Absorption-Modulator / Photo Detector (EAM/PD) pairs, were utilized for fulfilling reversible R gate. Then, reversible fulladder was designed based on the proposed reversible optical R gate. The operation of the suggested fulladder was simulated using Optispice and it was fou...

A study and comparison between current mode CMOS analog multiplier, CMOS current mode multiplier/divider and high frequency four quadrant current multiplier has been carried out in this paper. Current multiplier has been simulated in SPICE with 0.35μm, 0.5μm. Simulation have been done with supply voltage of 3.3V, 1.5V and 1.55V respectively. The simulated results show that characteristic of mul...

We show that the assumption n1 > λ in the Second Multiplier Theorem can be replaced by a divisibility condition weaker than the condition in McFarland’s multiplier theorem, thus obtaining significant progress towards the multiplier conjecture.