The paper suggests architecture of a reconfigurable processor, which can be customized for implementing different search algorithms over discrete matrices. Such algorithms might be used for solving various problems of combinatorial optimization, such as covering, Boolean satisfiability, etc. The proposed architecture contains memory blocks for a binary or a ternary matrix, general-purpose regis...

This paper presents the design alternatives for reconfigurable instruction set processors (RISP) from a hardware/software point of view. Reconfigurable instruction set processors are programmable processors that contain reconfigurable logic in one or more of its functional units. Hardware design of such a type of processors can be split in two main tasks: the design of the reconfigurable logic ...

Specific hardware customization for scientific applications has shown a big potential to address the current holy grail in computer architecture: reducing power consumption while increasing performance. In particular, the automatic generation of domain-specific accelerators for GeneralPurpose Processors (GPPs) is an active field of research to the point that different leading hardware design co...

Beam reconfigurable Transmitarray antennas require the unit cell phase variation capability. This paper presents a new design using PIN diodes at Ku-band. The is comprised of three layers having four used in every layer. results controlling by switching on layer individually. s-parametric analysis shows high transmission coefficient magnitude (> -3.6dB) frequency 12.5GHz and maximum wide imp...

Self-reconfigurable robots are designed so that they can change their external shape without human intervention. One general way to achieve such functionality is to build a robot composed of multiple, identical unit modules. If the modules are designed so that they can be assembled into rigid structures, and so that individual units within such structures can be relocated within and about the s...

In modern pervasive dynamic and eternal systems, software must be able to self-organize its structure and self-adapt its behavior to enhance its resilience and provide the desired quality of service. In this high-dynamic and unpredictable scenario, flexible and reconfigurable monitoring infrastructures become key instruments to verify at runtime functional and non-functional properties. In this...

Processors, from their inception, have been designed to heavily share a limited quantity of active hardware. This trend has continued to present, with modern microprocessors heavily multiplexing small execution engines making room to hold a large number of instructions and data on chip. As we look to the future, the real-estate available on a single VLSI IC continues to increase, shifting the p...

This paper describes an implementation of a novel systolic array for sequence alignment on the SPLASH reconfigurable logic array. The systolic array operates in two phases. In the first phase, a sequence comparison array due to Lopresti [2] is used to compute a matrix of distances which is stored in local RAM. In the second phase, the stored distances are used by the alignment array to produce ...