A low latency digit serial multiplier for GF(2m) that can be pipelined to the bit-level is presented in this paper. Unlike existing structures, the new multiplier does not put any restriction on the type of generator polynomial used or the digit size. Furthermore, the latency of the new multiplier is significantly less than the latency of the existing bit-level pipelined digit-serial multiplier...

assess the ecological effects of economic activity on the water, earth and man in the iranian economy approach using input - output tablewater is a vital resource for each biological and economic phenomenon. water is considered as a production input. production is not possible without water in all economic sectors. also, the environment including air, soil, fauna and plants utilize water in the...

Two interior-point algorithms are proposed and analyzed, for the (local) solution of (possibly) indefinite quadratic programming problems. They are of the Newton-KKT variety in that (much like in the case of primal-dual algorithms for linear programming) search directions for the “primal” variables and the Karush-Kuhn-Tucker (KKT) multiplier estimates are components of the Newton (or quasi-Newt...

In this article, we consider solvers for large-scale trust-region subproblems when the quadratic model is defined by a limited-memory symmetric rank-one (L-SR1) quasi-Newton matrix. We propose a solver that exploits the compact representation of L-SR1 matrices. Our approach makes use of both an orthonormal basis for the eigenspace of the L-SR1 matrix and the ShermanMorrison-Woodbury formula to ...

This work presents a convergence theory for a general class of trust-region-based algorithms for solving the smooth nonlinear programming problem with equality constraints. The results are proved under very mild conditions on the quasi-normal and tangential components of the trial steps. The Lagrange multiplier estimates and the Hessian estimates are assumed to be bounded. In addition, the regu...

A hybrid radix-4/radix-8 architecture targeted for high bit, general purpose, digital multipliers is presented as a compromise between the high speed of a radix-4 multiplier architecture and the low power dissipation of a radix-8 multiplier architecture. In this hybrid radix4/radix-8 multiplier architecture, the performance bottleneck of a radix-8 multiplier, the generation of three times the m...

1 Associate Professor, Department of Electronics and Communication Engineering, Nalla Narasimha Reddy Group of Institutions, Hyderabad, Telangana, India. 2 Assistant Professor, Department of Electronics and Communication Engineering, Nalla Narasimha Reddy Group of Institutions, Hyderabad, Telangana, India ---------------------------------------------------------------------***------------------...

This paper presents the design redundant Binary multiplier for 32*32bit number multiplication. Modern computer system is a dedicated and very high speed unique multiplier. Therefore, this paper presents the design a Redundant Binary multiplier. The proposed system generates M, N and interconnected blocks. By extending bit of the operands and generating an additional product the proposed system ...

This paper analyzes the power consumption of an array pipelined multiplier. To precisely realize a low power pipelined multiplier, the analytical model for a clocking system is presented. Simulation results show that the storage element is the key-component in a high performance pipelined multiplier macro. Compared with the conventional DFF and latch, the new low power DFF as PTTFF [6] achieves...

In this Paper, Urdhva tiryakbhyam Sutra is first applied to the binary number system and is used to develop digital multiplier architecture. This is shown to be very similar to the popular array multiplier architecture. This Sutra also shows the effectiveness of to reduce the NXN multiplier structure into an efficient 4X4 multiplier structures. Nikhilam Sutra is then discussed and is shown to b...