We present a novel floating-gate ultra lowvoltage (ULV) analog multiplicator with tunable linear range. Rail to rail operation is provided in the symmetric analog “gates” presented which are utilized in the ULV analog multiplier described in this paper.

The IEEE-754 floating-point standard, used in nearly all floating-point applications, is considered one of the most important standards. Deep datapath and algorithm complexity have made the verification of such floating-point units a very hard task. Most simulation and reachability analysis verification tools fail to verify a circuit with a deep datapath like most industrial floating-point unit...

SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled VDDs [8]. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results a...

A new technique for determining the parasitic source resistance in Heterostructure Field-Effect Transistors (HFET’s) is preManuscript received March 8, 1990; revised April 20, 1990. This work has been partially sponsored by an EECS Special Projects Fund from the MIT and by a TRW Scholarship from the MIT Undergraduate Research Opportunities Program. The review of this brief was arranged by Assoc...

A novel gate-all-around (GAA) poly-Si nanowire (NW) floating gate (FG) memory device was fabricated and characterized. The enhanced electric field around the corners of the nanowire channels boosts the P/E process and thus the operation voltages are dramatically lowered. Furthermore, the non-localized trapping feature characteristic of the FG makes the injection or ejection of electrons easier ...

We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detectable resistance, of intra-gate and inter-gate resistive shorts. We also propose a new keeper design for CMOS domino circuits. The new keeper design has low performance impact and is best useful for small CMOS domino g...

In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results i...

In this paper, we present a real–time noise suppression system implemented with analog VLSI. The algorithm implemented is designed to reduce stationary background noise in single– microphone signals while preserving the non–stationary signal component. Because the system relies on analog computation rather than digital, it has benefits such as extremely low power consumption and real-time compu...

The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated anten...

Self-timed circuits offer advantages over their synchronously clocked counterparts in a number of situations. However, self-timed design techniques are not widely used at present for a variety of reasons. One reason for the lack of experimentation with self-timed systems is the lack of commercially available parts to support this style of design. Field programmable gate arrays (FPGAs) offer an ...