BACKGROUND In the mid-1990s, Cochlear Corporation introduced a cochlear implant (CI) to the market that was equipped with hardware that made it possible to record electrically evoked compound action potentials (ECAPs) from CI users of all ages. Over the course of the next decade, many studies were published that compared ECAP thresholds with levels used to program the speech processor of the Nu...

My current interests span programming languages, compilers and computer systems, with emphasis on program optimization. Contrary to accepted views, the area of program optimization is broad, multifaceted, almost interdisciplinary. Its spectrum extends from compiler optimization to the more experimental processor architecture and to the more formally treated program specialization. While my thes...

In the last fifteen years many work in logic programming has focussed on parallel implementations both in shared memory and in distributed memory multiprocessor systems. In both cases it is supposed that each processor knows the entire logic program. In this paper we shall study a case where each agent only knows part of the program. We give a multi-modal logical language and its semantics whic...

For the increasing demands of computation, heterogeneous multicore architecture is believed to be a promising solution fulfill edge computational requirement. In FPGAs, realized as multiple soft processor cores with custom processing elements. Since FPGA resource-constrained device, sharing hardware resources among can advantageous. A few research works have focused on resource between processo...

This paper describes a distributed performance monitoring system for a transputer-based multiprocessor, Hathi-2. The monitoring system allows the programmer to measure how well a parallel program utilizes the hardware resources of the multiprocessor system, i.e., the processor CPU’s and communication links, during program execution. It can be used for identifying performance bottlenecks in para...

This paper concerns a general executive program for the Burroughs D825 Modular Data Processing System. The D825 is a large-scale, multicomputer, expansible, general-purpose, digital system employing automatic parallel processing and an extensive system of interrupts, and is especially suited to military command and control applications. Military designation is AN/GYK-3 (V). The implementation o...

The Tera MTA (for \Multithreaded Architecture") computer features a radically new architecture, with hardware support for up to 128 threads per processor, a powerful instruction set, nearly uniform access time to all memory locations, and zero-cost synchronization and swapping between threads of control. Memory access latencies are tolerated by swapping between the threads. Given a multithreade...

To program a processor, you need to have some model of how it behaves. But providing accurate functional models of processors is challenging. Traditionally, the behavior of a processor is specified by documentation that describes its Instruction Set Architecture, or ISA. This documentation is usually long, making it laborious to produce, and it is often riddled with errors, typos, and inconsist...

The primary goal of processor scheduling is to assign tasks in a parallel program to processors, so as to minimize the execution time. Most existing approaches to processor scheduling for multiprocessors assume that the execution time of each task is xed and is independent of processor scheduling. In this paper, we argue that the execution time of a given task is not xed but is critically depen...