TCP’s poor performance is identified as the bottleneck of high-speed networks. Extensions to TCP have been proposed and implemented. Some authors abandon TCP at all and suggest new transport protocols to overcome TCP limitations, at the expense of compatibility. This paper reports a research on the most significant TCP extensions and transport alternatives, and comparison between them. The majo...

For many digital designs, implementation in passtransistor logic (PTL) has been shown to be superior in terms of area, timing, and power characteristics to static CMOS. Binary Decision Diagrams (BDDs) have been used for PTL synthesis because of the close relationship between BDDs and PTL. Thus far, BDD optimization for PTL synthesis has targeted minimizing the number of BDD nodes. This strategy...

| In this work we present generic low power techniques for minimizing the energy-delay product for CMOS digital circuits. These techniques, which optimize and use multiple or variable power supply and threshold voltages and transistor sizing, are presented according to their application to diierent classes of circuits along the space and time dimensions.

We first present a circuit taxonomy along the space and time dimensions, which is useful for classifying generic low-power techniques, followed by an analysis of optimal power supply and threshold voltages and transistor sizing for minimizing the energy-delay product of a class of complementary metal–oxide–semiconductor (CMOS) digital circuits.

Full adders are essentially used as a building block in all arithmetic, DSP and microprocessor applications. In this paper, a 15 transistor hybrid PTL-TG full adder circuit is proposed. The main objective is to provide high speed, low power, full swing operation with good drivability. The choice of logic design affects the circuit performance. The delay time depends on the number of transistors...

The L1 data cache is a time-critical module and, at the same time, a major source of energy consumption. To reduce its energy-delay product, we apply two principles of low power design: specialize part of the cache structure and break down the cache into smaller caches. To this end, we propose a L1 cache that combines new designs of a stack cache and a PSA cache. Individually, our stack and PSA...

Background: At present scenario, the frequent and the most fundamental component in low power processor design is Arithmetic and Logic Unit (ALU). Further Power utilization due to clock gated ALU can be noteworthy in high performance systems. In general functionality of the ALU's is a mixture of arithmetic and logic operations which are realized by means of combinational circuits. In attendance...

Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In ...

a graph of size n is said to be graceful when is possible toassign distinct integers from {0, 1, . . . , n} to its verticesand {|f(u)−f(v)| : uv ∈ e(g)} consists of n integers. inthis paper we present broader families of graceful graphs; these families are obtained via three different operations: the third power of a caterpillar, the symmetric product of g and k2 , and the disjoint :union: of g...