In this paper fast pipelined digit-serial/parallel multipliers are proposed. The conventional digit-serial/parallel multipliers and their pipelined versions are presented. Every structure has been implemented on FPGA and the results are given. These results have been analysed and it is detected that the pipelined ones do not have the throughput improvement expected because of a logic depth incr...

Multiplier is one of the most inevitable arithmetic circuit in digital signal design. Multipliers dissipate high power and occupy significant amount die area. In this paper, a low-error architecture design pre-truncated parallel multiplier presented. The coefficients word length has been truncated to reduce size. This truncation scaled down gate count shortened critical paths partial product ar...

This paper describes in detail the design of a CMOS custom fast Fourier transform (FFT) processor for computing a 256-point complex FFT. The FFT is well-suited for realtime spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor reported here consists of one parallel–parallel multiplier and two adders. It is capable of computing one butterfly computation e...

The multiplication operation is present in many parts of a digital system or digital computer, most notably in signal processing, graphics and scientific computation. With advances in technology, various techniques have been proposed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speeds, low power compact VLSI imp...

In many multimedia and digital-signal processing (DSP) applications, multipliers are considered to be the basic arithmetic units. These multipliers significantly influence the system’s performance and power dissipation. To achieve high performance, the modified Booth encoding has been widely adopted in parallel multipliers. It reduces the number of partial products through performing multiplier...

This paper describes in detail the design of a custom CMOS Fast Fourier Transform(FFT) processor for computing 256-point complex FFT. The FFT is well suited for real-time spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor consists of one parallel-parallel multiplier and two adders. It is capable of computing one butterfly computation every 100ns thus ...

This paper presents research results related to the concept of a high-voltage-gain DC-DC converter with low input current ripple. In proposed topology, low-volume switch-mode boost operates in parallel switched-capacitor voltage multiplier (SCVM). The overall achieves four-fold gain, but stress transistor and diode is only half output voltage. achieved by applying specific topology converter. F...

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the followinghigh speed, low power consumption, regularity of layout and hence less area or even combination of them ...

In this paper, We propose an algorithm and architecture of a BCD parallel multiplier that exploits some properties of two different redundant BCD codes to speed up its computation. In this paper, we also develop new techniques to reduce the latency and area of previous representative high performance implementations. The Partial products are generated in parallel using a signed-digit radix-10 r...