Instruction-Level Redundancy (ILR) is a well known approach to tolerate transient CPU faults. It replicates instructions in a program and inserts periodic checks to detect and correct CPU faults using majority voting, which essentially requires three copies of each instruction and leads to high performance overheads. As SIMD technology can operate simultaneously on several copies of the data, i...

In this paper, we present a pointer and array access checking technique that provides complete error coverage through a simple set of program transformations. Our technique, based on an extended safe pointer representation, has a number of novel aspects. Foremost, it is the rst technique that detects all spatial and temporal access errors. Its use is not limited by the expressiveness of the lan...

High capacity and scalable memory systems play a vital role in enabling our desktops, smartphones, and pervasive technologies like Internet of Things (IoT). Unfortunately, memory systems are becoming increasingly prone to faults. This is because we rely on technology scaling to improve memory density, and at small feature sizes, memory cells tend to break easily. Today, memory reliability is se...

Automatic parallelization has become a mainstream research topic for different reasons. For example, multicore architectures, which are now present even in laptops, have awakened an interest in software tools that can exploit the computing power of parallel processors. Distributed and (multi)agent systems also benefit from techniques and tools for deciding in which locations should processes be...

With High Performance Computing moving towards Exascale, where parallel applications will be required to run concurrently on millions of cores, every part of the computational model must perform ideally to achieve optimal performance. The task scheduler is one of such entities that could be enhanced to runtime application prerequisites. Not only the overheads associated with task scheduling var...

The overheads associated with feedback-based channel acquisition can greatly compromise the achievable rates of FDD based massive MIMO systems. Indeed, downlink (DL) training and uplink (UL) feedback overheads scale linearly with the number of base station (BS) antennas, in sharp contrast to TDDbased massive MIMO, where a single UL pilot trains the whole BS array. In this work, we propose a gra...

The field of lightweight cryptography has developed significantly over recent years and many impressive implementation results have been published. However these results are often concerned with a core computation and when it comes to a real implementation there can be significant hidden overheads. In this paper we consider the case of cryptoGPS and we outline a full implementation that has bee...

In this work we present a microbenchmark methodology for assessing the overheads associated with nested parallelism in OpenMP. Our techniques are based on extensions to the well known EPCC microbenchmark suite that allow measuring the overheads of OpenMP constructs when they are effected in inner levels of parallelism. The methodology is simple but powerful enough and has enabled us to gain int...

Software DSM systems su er from the high communication and coherence-induced overheads that limit performance. This paper introduces our e orts in reducing system overheads of a home-based software DSM called JIAJIA. Three measures, including eliminating false sharing through avoiding unnecessarily invalidating cached pages, reducing virtual memory page faults with a new write detection scheme,...

Mobile code carried by a mobile agent can automatically travel to several data sources in order to complete a designated program. Traditionally, most mobile agent systems [7][8][13] need explicit involvement of the programmer to designate migration and computation schedule of the agent. In this paper, we study the compilersupported agent scheduling to optimize either the number of the migration...