ÐA class of highly scalable interconnect topologies called the Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) is proposed. This proposed class of networks combines the use of tunable Vertical Cavity Surface Emitting Lasers (VCSEL's), Wavelength Division Multiplexing (WDM) and a scalable, hierarchical network architecture to implement large-scale optical crossbar based netw...

Opto-electronic reconfigurable interconnection networks are limited by significant control latency when used in large multiprocessor systems. This latency is the time required to analyze the current traffic and reconfigure the network to establish the required paths. The goal of latency hiding is to minimize the effect of this control overhead. In this paper, we introduce a technique that perfo...

Application specific architectures are highly desirable in embedded parallel computing systems at the same time as designers strive for using one embedded parallel computing platform for several applications. If this can be achieved the cost can be decreased in comparison to using several different embedded parallel computing systems. This paper presents a novel approach of running several high...

w ith device characterist ics approaching physical limits, parallel or distributed processing has been widely advocated as a promising approach for building high performance computing systems. The continued impetus in research in these areas arises from two factors: (a) the technological development in the areaof VLSI chips and (b) the observation that significant exploitable software paralleli...

This paper presents the architecture of a special-purpose multiprocessor system, which we call the Broadcast Cube System (BCS), for solving non-linear Partial Differential Equations (PDEs). The BCS has the following important features: (a) Being based on the conceptually simple bus interconnection scheme it is easily understood. The use of homogeneous Processing Elements (PEs) which can be real...

Network processors have great potential to combine high performance with increased flexibility. These multiprocessor systems consist of programmable elements, dedicated logic, and specialized memory and interconnection networks. However, the architectural complexity of the systems makes programming difficult. Programmers must be able to productively implement high performance applications for n...

Sung Woo Chung is the designated presenter and he will attend the conference should his paper accepted Primary technical subject area : A. Computer Architecture and Super Computing 1. Introduction As microprocessors speeds continue to improve at a very fast rate the bandwidth requirements for system level interconnections in multiprocessor systems rule out the use of shared buses even for small...

[6] W. J. Dally, " Performance Analysis of k-ary n-cube interconnection networks, " IEEE Transactions on Computers, June 1990.

We present several optical interconnection structures which support communication requirements unique to multiprocessor systems, namely, broadcasting, multicasting, simulcasting, and multiport memory access. The structures are based on guided wave time division multiplexed channels and use coincident pulse techniques to optically demultiplex individual bits at selected destinations. We describe...

Today, even the simplest laptop processor has at least four cores and a graph-ics card containing tens of cores. It is not hard to find more performance-oriented processors with hundreds of cores, and it is expected to see proces-sors with thousands of cores in the not very far future.In these and future processors, the design of the interconnection networkbetween the cores ...