Multicore architecture otherwise called as SoC consists of large number of processors packed together on a single chip uses hyper threading technology. This increase in processor core brings new advancements in simultaneous and parallel computing. Apart from enormous performance enhancement, this multicore platform adds lot of challenges to the critical task execution on the processor cores, wh...

Three studies investigated (a) the plausibility of the claim that increasing the processing demands in a memory task contributes to greater involvement of a central processor and (b) the effects of altering reliance on the central processor on the magnitude of age-related differences in working-memory tasks. In the first study, young adults performed versions of 2 tasks presumed to vary in the ...

To address the increasingly important energy efficiency problem, a Standby-Sparing scheme has been studied previously to reduce the energy consumption in dual-processor fault-tolerant systems. However, the dedicated (spare) processor in the Standby-Sparing scheme needs to execute backup tasks at full speed to preserve system reliability and thus cannot effectively exploit its available slack ti...

In this paper we present Pepsy, a novel prototyping environment for multiDSP systems, with the primary goal to support the design and implementation of parallel digital signal processing (DSP) applications subject to various design constraints. Given a specification of the prototyping problem in the form of an application model, a hardware model and mapping constraints, Pepsy automatically maps...

This paper addresses resource reclaiming in the con text of non preemptive priority list scheduling for hard real time systems Such scheduling is inherently suscep tible to multiprocessor timing anomalies We present low overhead run time stabilization methods for a gen eral tasking model that allows phantom tasks as a mech anism to model processor external events A family of scheduling algorith...

Responsive Multithreaded (RMT) Processor that controls thread execution in Simultaneous Multithreading by introducing thread priority has been invented for parallel and distributed real-time processing. This paper concerns the basic approach of real-time scheduler on RMT processor. Our goal is to build a system where various types of tasks reside; hard/soft real-time tasks, periodic/aperiodic t...

With the development of high-performance computing, it is possible to solve large-scale computing problems. However, irregularity and access characteristics problems bring challenges realisation performance optimisation. Improving a single core makes challenging maintain Moore's law, multi-core processors emerge. A chip brings together multiple universal processor cores equal status has same st...

Pattern-Oriented Application Frameworks for Domain Experts to Effectively Utilize Highly Parallel Manycore Microprocessors

This paper presents a proposed architecture for constructing a conventional-quantum computing machines from the hardware point of view. The proposed architecture will help in improving the performance of the conventional computer by building a new processor; such processor combines both a classical processor in conjunction with a Co-quantum processor. The proposed architecture classifies the op...

We show the NP-Completeness of two processor scheduling with tasks of execution time 1 or 2 units and unit interprocessor communication latency. We develop a model of scheduling in the presence of communication contention, and show the NP-Completeness of two processor scheduling with unit execution time tasks in our model.