Simple COMA is a method for sharing address spaces among different nodes of a distributed memory computer. This method provides high performance without the complex and costly changes required by other shared memory organizations. It also retains the positive attributes of a distributed memory multicomputer, such as scalability and high availability. This paper explains the Simple COMA shared m...

In this paper a new orthogonal partially shared memory architecture for the design of multiprocessor systems is proposed. The architecture allows processors to partially share a 2-D array of memory modules in an orthogonal way with less limitations than those imposed by the traditional orthogonal (OMP) architecture. Processors have direct access to large neighborhoods of memory modules which ca...

In this paper we propose a new orthogonal partially shared memory architecture for the design of multiprocessor systems. The architecture allows processors to partially share a 2-D array of memory modules in an orthogonal way with less limitations than those imposed by the traditional orthogonal (OMP) architecture. Processors have direct access to large neighborhoods of memory modules which can...

Commodity microprocessors contain more on-chip memory with each successive generation, and will contain tens of megabytes within the decade. We describe a novel architecture that runs an unmodified uniprocessor program across multiple nodes, each of which contains a processor tightly integrated with a sizable memory. The execution of instructions is replicated, while the access of operands is d...

Morphine’s effects on learning and memory processes are well known to depend on synaptic plasticity in the hippocampus. Whereas the role of the hippocampus in morphine-induced amnesia and state-dependent learning is established, the biochemical and molecular mechanisms underlying these processes are poorly understood. The present study intended to investigate whether administration of morphine ...

This paper presents a motion compensation architecture for QuadHD H.264/AVC video decoder. For meeting the high throughput requirement, reducing power consumption and solving the memory latency problems, three optimization schemes are applied in this work. Firstly, a quarter-pel interpolator based on HorizontalVertical Expansion and Luma-Chroma Parallelism (HVE-LCP) is proposed to efficiently i...

Despite its successes, Rumelhart and McClelland's (1986) well-known approach to the learning of morphophonemic rules suffers from two deficiencies: (1) It performs the artificial task of associating forms with forms rather than perception or production. (2) It is not constrained in ways that humans learners are. This paper describes a model which addresses both objections. Using a simple recurr...

In-memory computing (IMC) aims to solve the performance gap between CPU and memories introduced by memory wall. However, it does not address energy wall problem caused data transfer over hierarchies. This paper proposes data-locality management unit (DMU) efficiently from a DRAM computational SRAM (C-SRAM) allowing IMC operations. The DMU is tightly coupled within C-SRAM allows one align struct...

Embedded systems are typically designed for one or a few target applications, allowing for customization of the system architecture for the desired system goals such as performance, power and cost. The memory subsystem will continue to present significant bottlenecks in the design of future embedded systems-on-chip. Using advance knowledge of the application’s instruction and data behavior, it ...