A bstract We formulate an alternative approach based on unitarity triangles to describe neutrino oscillations in presence of non-standard interactions (NSI). Using perturbation theory, we derive the expression for oscillation probability case NSI and cast it terms three independent parameters leptonic triangle (LUT). The form invariance (even new physics scenario as long mixing matrix is unitar...

Interconnections are increasingly one of the dominant contributors to delay, area and energy consumption in CMOS digital circuits now a days. Multiple Valued Logic (MVL) can decrease the average power required for level transitions and also the number of required interconnections are reduced. So the impact of interconnections on overall energy consumption is reduced. In this paper, a quaternary...

This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance and power of the Tree-bas...

This paper presents an optimized synchronous hybrid scaling scheme for the 8-bit moduli set {2 − 1,2,2 + 1}. Both Look-up-tables (LUTs) and modular adders are employed efficiently to generate the accurate scaled residues. Reverse conversion from residues to the original binary number is also computed in one residue channel without further hardware cost required. Xilinx device xc6slx4 − 3tqg144 ...

This paper presents a method for synthesizing lookup table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods; many decomposition methods that are not only algebraic but also functional are integrated very well. Our method can be thought of as a general framework for LUT network synthesis integrating various decomposition methods. The e...

Introduction Altera continues to lead the FPGA industry in architectural innovation. The logic fabric and routing architecture in Altera® FPGAs are unmatched, providing customers with a number of advantages. Altera was the first to introduce the 8-input fracturable look-up table (LUT) with the Stratix® II family in 2004. At its core is the adaptive logic module (ALM) with 8 inputs, which can im...

Among many existing algorithms, convergence methods are the most popular means of computing square root and the reciprocal of square root of numbers. An initial approximation is required in these methods. Look up tables (LUT) are employed to produce the initial approximation. In this paper a number of methods are suggested to reduce the size of the look up tables. The precision of the initial a...

Turbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate a low transmission energy consumption. However, in order to reduce the overall energy consumption, lookup table-log-BCJR (LUT-Log-BCJR) architectures having a low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its...

An address generator produces a unique address from 1 to k when the input that matches one of k registered vectors, and produces 0 for other inputs. This paper presents a method to design an address generator using a hash memory and an LUT cascade. The hash memory realizes about 90% of the registered vectors, while the LUT cascade realizes the remaining 10% of the registered vectors. This metho...