This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic partitioning, floorplanning, global routing, and timing analysis/budgeting steps, followed by technology remapping and detailed placement of the selected logic clusters. The strength of the approach lies in the dynamic programming...

Asynchronous Fine-grain power gated Logic (AFL) which includes Modified Efficient Charge Recovery Logic (M-ECRL) gates to implement the logic function of the stage with a handshake controller which comprises of C-element to handle the control signals with the neighboring stages and provides power to MECRL gate. AFL adopts an partial charge reuse (PCR) mechanism, part of the charge on the output...

— Memristors are passive components with a varying resistance which depends on the previous voltage applied across the device. While memristors are naturally used as memory, memristors can also be used for other applications, including logic circuits. In this paper, a memristor only logic family, MAGIC (Memristor Aided LoGIC), is presented. In each MAGIC logic gate, memristors serve as an input...

This paper aims at reducing power and energy dissipation in Transmission Gate Logic (TGL) Multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply current and delay with economical charge recovery logic. This paper designs an 8:1 Multiplexer with CMOS Transmission Gate Logic (TGL) using the Power Gating Technique, which reduces the leakage power and leakage current...

Power dissipation is one of the important factor in digital circuit design. Landauer's principle states that logic computations which are not reversible necessarily generate KT*ln2 Joules of heat energy for every bit of information that is lost, where k is Boltzmann's constant and T the absolute temperature at which computation is performed. Reversibility is the property of digital circuits in ...

In this paper we investigate single electron tunneling (SET) devices from the logic design perspective, using the SET tunnel junction’s ability to control the transport of individual electrons. More in particular, we investigate the behavior of a family of single electron encoded logic (SEEL) gates, consisting of a 2-input AND gate, a 2-input OR gate and a NOT gate, and simulate the gates. A ch...

This work demonstrates two DNA-based logic circuits that behave as a half-adder and a half-subtractor. A half-adder is composed of an AND gate and an XOR gate, whereas a half-subtractor consists of an INH gate and an XOR gate. The proposed designs are inspired by molecular beacons.

We present designs of reversible Peres logic gate and FeynmanDouble logic gate based on all-optical switching by two-photon absorption induced free-carrier injection in silicon add-drop microring resonators. The logic gates have been theoretically analyzed using time-domain coupled-mode theory and all-optical switching has been optimized for low-power (25 mW) ultrafast (25 ps) operation with hi...

Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional correctness of a circuit but also speed independence, i.e., hazard freedom under unbounded gate delays. This paper presents a new method for logic decomposition of speed-indep...

A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-ofproduct and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynami...