It has become clear that large embedded configurable memory arrays will be essential in future field programmable gate arrays (FPGA’s). Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for cus...

The division of a monolithic neural network into blocks with their implementation on programmable logic within the framework Fog computing concept is considered. It assumed that considering possible reconfiguration performed logic: field-programmable gate array, FPGA (complex device, CPLD), System-on-a-Chip, SoC or System-in-Package, SiP. article explores such an in Proteus Design Suite based A...

Two major problems that arise in parallel logic programming systems are: (i) redundant computation during and-parallel execution of dependent goals, and, (ii) eecient representation of multiple environments at runtime. Both these problems are caused by non-determinism present in logic programs|responsible for much of the power of logic programming. This paper is mainly concerned with solving th...

As intended by its name, Physically Unclonable Functions (PUFs) are considered as an ultimate solution to deal with insecure storage, hardware counterfeiting, and many other security problems. However, many different successful attacks have already revealed vulnerabilities of certain digital intrinsic PUFs. This paper demonstrates that legacy arbiter PUF and its popular extended versions (i.e.,...

In this paper, the concepts of car maneuvers, fuzzy logic control (FLC), and sensor-based behaviors are merged to implement the human-like driving skills by an autonomous car-like mobile robot (CLMR). Four kinds of FLCs, fuzzy wall-following control, fuzzy corner control, fuzzy garage-parking control, and fuzzy parallel-parking control, are synthesized to accomplish the autonomous fuzzy behavio...

In the paper the programmable logic array (PLA) topological optimization problem is dealt with using folding techniques. A PLA folding algorithm based on the method of simulated annealing is presented. A simulated-annealing PLA folding algorithm is presented for multiple unconstrained folding. Then, the algorithm is extended to handle constrained folding. In this way, simple folding is consider...

ÐAn FPD switch module M with w terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most w) is simultaneously routable through M [8]. Chang et al. have identified a class of universal switch blocks in [8]. In this paper, we consider the design and routing problems for another popular model of sw...

A universal literal is a single-variable function and has an ability to manipulate more information than a set lateral. The array size therefore could be eliminated b y using universal literal generators (ULGs for short) in programmable logic arrays (PLAs), compared to PLAs with set literals. This paper discusses what operator is the most suitable in the term of eliminating the array size. We f...

Two micro crystal element (MiCE) detector unit designs are evaluated. The detector units are built using highly packed arrays of 0.8 0.8 6 mm mixed lutetium silicate (MLS) crystals. The first detector unit, MiCE1, consists of a 5 5 array of 0.8 mm 0.8 mm 6 mm MLS crystals. The detector unit is coupled to four channels of a Hamamatsu multichannel photomultiplier tube (PMT) via a 2 2 array of 2 m...