[1] We first define the phase volume of a system as the volume contained within the energy surface in the phase space and define its phase density as its derivative with respective to energy. Because of the ergodic hypothesis, the system phase density can be obtained as the convolution product of the phase densities of the individual parts; and these can again, when the energy of the parts can ...

We proposed a 24-GHz frequency synthesizer (FS) for automotive radar application, which consists of a phaselocked loop (PLL) and an injection-locked frequency multiplier (ILFM). Based on a novel topology, the multiply-by2 ILFM consists of a double-balanced mixer and an injectionlocked oscillator (ILO). The PLL is designed with a 12-GHz voltage-controlled oscillator (VCO) and an injection-locked...

The γ-optimization parameter is one of the key parameters for designing loop filters of phase-locked loop and optimal choice of γ depends on phase margin of the system. Here, we propose to study the impact of γ-optimization parameter and phase margin on closed loop gain of phase-locked loop for frequency synthesizer. A model has been developed and simulated, considering two different filter sec...

Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) is used to linearize the phase difference detection, and enhance the loop performance. The loop has faster acquisition, less steady state phase error, and wider locking range compared to the conventional ZCDPLL. This work presents a Zero Crossing Digital Phase Locked Loop with Arc Sine block (ZCDPLL-AS). The performance of ...

The PLL equivalent augmented system incorporated with state feedback is proposed in this paper. The optimal value of filter time constant of loop filter in the phase-locked loop control system and the optimal state feedback gain designed by using linear quadratic regulator approach are derived. This approach allows the PLL control system to employ the large value of the phasefrequency gain d K ...

This paper present area efficient layout designs for 3.3GigaHertz (GHz) Phase Locked loop (PLL) with four multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output, using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, sw...

The traditional analog signal processing is expected to progressively substituted by the processing times of the digital domain in the VLSI .Within this novel paradigm ,digitally controlled delay lines should play the vital role in the digital-toanalog converters ,and in analog intensive circuits. From a practical point of view, nowadays, DCDL is a key block in the many applications like All Di...

In this paper, a multipath mitigation tracking system is presented for static GPS applications. It is comprised of four function blocks, those being (1) adaptive path estimator (APE), (2) multipath interference reproducer (MPIR), (3) Rake-based delay locked loop (RB-DLL), and (4) Rake-based phase locked loop (RB-PLL). Only the short delay condition with delay less than 1.5 PN chip is considered...

The control system of a doubly-fed adjustable-speed pumped-storage hydropower plant needs phase-locked loops (PLLs) to obtain the phase angle of grid voltage. The main drawback of a comb-filter-based phase-locked loop (CF-PLL) is the slow dynamic response. This paper presents a modified comb-filter-based phase-locked loop (MCF-PLL) by improving the pole-zero pattern of the comb filter, and give...