In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression drive...

Gallium arsenide junction field-effect transistors (GaAs JFETs) can be made immune to carrier freeze-out, making such transistors useful for the readout of detector arrays that operate at 4 K. Typical applications require transistors with very low noise and extremely low leakage current. By using a recently developed etchant for GaAs that is highly isotropic, etched GaAs JFETs have fabricated t...

1PG Scholar, Department of EEE, Sri Shakthi Institute of Engineering and Technology, Tamilnadu, Indian 2Assistant Professor, Department of EEE, Sri Shakthi Institute of Engineering and Technology, Tamilnadu, Indian ---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Due to the decade of fossil fuel ...

Two types of thin septum magnets, direct drive and eddy current, were c mainly in 2-D magnetic aspects. For the direct-drive type, the leakage field depend finite permeability of the magnet core and not on the thickness of the septum conduct suggested that the leakage field be controlled by reducing the current in the septum c or by using a correction coil. There were no significant differences...

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in powe...

Reducing the ever-growing leakage current is critical to high performance and power efficient designs. We present an in-depth study of high-level leakage modeling and reduction in the context of a full custom design environment. We propose a methodology to estimate the circuit area, minimum and maximum leakage current, and maximum power-up current, introduced by leakage reduction using sleep tr...

Supply voltages and threshold voltages continue t o be aggressively scaled down in order t o obtain power reduction, performance improvement, and increasing integration density. This leads to leakage current becoming a much more significant component of power than it has been in the past. We have previously shown that substantial leakage reduction can be achieved in single Vt circuits by turnin...

This paper aims at reducing power and energy dissipation in Transmission Gate Logic (TGL) Multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply current and delay with economical charge recovery logic. This paper designs an 8:1 Multiplexer with CMOS Transmission Gate Logic (TGL) using the Power Gating Technique, which reduces the leakage power and leakage current...

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirem...