Abstract Background: Several studies have examined the reflex response of ankle musculature to sudden inversion in noninjured and injured subjects. To date, there have been no studies to determine the effect of versatile degrees & conditions of perturbation on the ankle musculature latency. The purpose of this study was to measure and determine whether there was a difference in ankle musculatu...

This paper presents a multi-level memory prefetch hierarchy for media and stream processing applications. Two major bottlenecks in the performance of multimedia and network applications are long memory latencies and limited off-chip processor bandwidth. Aggressive prefetching can be used to mitigate the memory latency problem, but overly aggressive prefetching may overload the limited external ...

Hardware data prefetcher engines have been extensively used to reduce the impact of memory latency. However, microprocessors’ hardware prefetcher engines do not include any automatic hardware control able to dynamically tune their operation. This lacking architectural feature causes systems to operate with prefetchers in a fixed configuration, which in many cases harms performance and energy co...

To increase the bandwidth of synchronous memories that are widely adopted for HDTV decoder systems, a predictive mode control scheme is proposed in this paper. Memory latency and energy consumption can be reduced by effectively managing the states of banks. The local access history of each bank is considered to predict the memory mode. In a HDTV decoder system, experimental results show that th...

OF THE DISSERTATION Using Multithreaded Techniques to Mask Memory Latency on FPGA Accelerators

The efficient use of bandwidth available on an external SDRAM interface is strongly dependent on the sequence of addresses requested. On-chip memory buffers can make possible data reuse and request reordering which together ensure bandwidth on an SDRAM interface is used efficiently. This paper outlines an automated procedure for generating an application-specific memory hierarchy which exploits...

A prominent challenge in the support of Wide Area Applications (WAA) involves their unpredictable behavior over a dynamic WAN that results in a considerable variability in access latency (end-toend delay). Latency profiles capture the changing latencies that clients experience when accessing a server and can be utilized as a WAA monitoring and optimization tool. However, in the presence of hund...

increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...