1 Embedded real-time applications that interact with the outside environment may be subjected to temporal uncertainty due to the potential asynchronous characteristics of events. If event handling, which is usually associated with interrupts, is not carefully controlled, overload scenarios can cause application tasks to miss deadlines, with severe consequences. In this paper we address the prob...

In this paper, we present and verify a new model designed to capture the benefits of protocol offload in the context of high performance computing systems. Other models capture the benefits of offload or the performance of parallel applications. However, the extensible message-oriented offload model (EMO) is the first model to emphasize the performance of the network protocol itself and models ...

In the paper, a concept and an early analysis of an HW/SW architecture designed to prevent the SW from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the HW (SW) part of an application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt interrupt service rates to the a...

The concept of an interrupt is one that appears across many paradigms, and used in many different areas. It may be used as a device to assist specifications to model failure, or to describe complex interactions between non co-operating components. It is frequently used in hardware to allow complex scheduling patterns. Although interrupts are ubiquitous in usage, the precise behaviour of a syste...

Safety critical systems and in particular higher functional integrated systems like mixed-criticality systems in avionics require a safeguarding that functionalities cannot interfere with each other. A notably underestimated issue are I/O devices and their (message-signaled) interrupts. Message-signaled interrupts are the omnipresent type of interrupts in modern serial high-speed I/O subsystems...

The effects of the general-purpose precise interrupt mechanisms in use for the past few decades have received very little attention. When modern out-of-order processors handle interrupts precisely, they typically begin by flushing the pipeline to make the CPU available to execute handler instructions. In doing so, the CPU ends up flushing many instructions that have been brought in to the reord...

There has been significant progress making standard Linux into a more responsive system for real-time applications. The low latency patches and the preemption patches have allowed guarantees on worst case interrupt response time at slightly above a millisecond. These guarantees today are only met when there is no networking or graphics activity in the system. The shielded processor concept dedi...

doi:10.3949/ccjm.83a.15014 W i was growing up, my mother frequently told me that it was rude to interrupt. Although she was referring to conversations, she may have been onto something bigger. In the nearly three quarters of a century since their discovery, vitamin K antagonist anticoagulant drugs have been used by millions of patients to prevent heart attack and stroke. Before these patients u...

This paper describes and evaluates solutions to the precise interrupt problem in pipelined processors. An interrupt is precise if the saved process state corresponds with a sequential model of program execution where one instruction completes before the next begins. In a pipelined processor, precise interrupts are difficult to implement because an instruction may be initiated before its predece...