A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these mod...

In this paper, we performed the comparative analysis of power consumption of array multiplier circuit implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 10 transistorStatic Energy Recovery CMOS adder and 8 transistor CMOS (SERF) circuits. At first, the circuit was simulated with adder modules without applying the SVL circuit. And se...

In digital VLSI systems binary addition is the most significance arithmetic function. To a great extent adders are used as DSP lattice filter where the ripple carry adders are substituted by the parallel prefix adder to reduce delay. The requirement of adder is that it is fast and it has area efficient and low power consumption. In this the parallel prefix adder is introduced as speculative Han...

Reversible circuits have applications in digital signal processing, computer graphics, quantum computation and cryptography. In this paper, a generalized k*k reversible gate family is proposed and a 3*3 gate of the family is discussed. Inverter, AND, OR, NAND, NOR, and EXOR gates can be realized by this gate. Implementation of a full-adder circuit using two such 3*3 gates is given. This full-ad...

This paper presents the design, the analysis and the complete characterization of a novel split-path Data Driven Dynamic (sp-D3L) full adder cell in IBM’s 65 nm CMOS process. The split path D3L design style derived from standard D3L allows the design of high speed dynamic circuits without the power overhead of the clock tree while providing significantly higher performance than the D3L due to r...

In this paper, a novel 3-moduli set { 2 − 1, 2, 2 − 1 } , which has larger dynamic range when compared to other existing 3-moduli sets is proposed. After providing a proof that this moduli set always results in legitimate RNS, we subsequently propose an associated reverse converter based on the New Chinese Remainder Theorem. The proposed reverse converter has a delay of (4n + 6)tFA with an area...

This paper is devoted for the design and implementation of a 32bit Arithmetic module it is used for vedic Mathematics algorithms. We have various arithmetic multiplication techniques like Urdhva, Tiryakbhyam, Nikhilam, and Anurupye has been thoroughly analyzed. A 32 x 32 bit multiplier using Urdhava Tiryakbhyam, it has been designed and using this multiplier, a MAC unit has been designed. An Ar...

A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) b...

Energy recovery technique has attracted interest of low power VLSI designers in recent years. This low power design technique has been proposed and discussed by many researchers. In this paper, we implemented energy recovery technique in the PSPICE using an 8-bit full adder circuit as an example. Full adder circuit has been widely used in arithmetic operations for addition, multipliers and Arit...