Postprocessing annealing in forming gas at 400 ◦C was performed on enhancement-mode lattice-matched InAlN/AlN/GaN high-electron-mobility transistors fabricated by selective etch of InAlN under a Pt gate. After postprocessing annealing, the device reverse gate leakage current decreased from 10−7 to 10−12 A/mm at Vgs = −1 V and Vds = 6 V, showing an ON/OFF current ratio of 10 that is the highest ...

In this paper, a new configuration for symmetrical and asymmetrical multilevel inverters is proposed. In asymmetric mode, different algorithms are suggested in order to determine the magnitudes of DC voltage sources. The merit of this topology to the conventional symmetric and asymmetric inverters is verified by the provided comparisons. This topology uses a lower number of power electronic dev...

We study the weight dynamics of the floating-gate pFET synapse and the effects of the pFET’s gate and drain voltages on these dynamics. We show that we can derive a weight update rule such that the equilibrium weight value is proportional to the correlation between the gate and drain voltages. In particular, we want a rule of the form _ = + [ ], where is a voltage signal on the gate terminal an...

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increase...

For the first time, we demonstrate experimentally that by using HfLaO high-κ gate dielectric, the flat-band voltage (Vfb) and the threshold voltage (Vth) of metal-electrode-gated MOS devices can be tuned effectively in a wide range (wider than that from the Si-conduction band edge to the Si-valence band edge) after a 1000-◦C annealing required by a conventional CMOS source/drain activation proc...

A single-electron memory, in which a bit of information is stored by one electron, is demonstrated at room temperature. The memory is a floating gate metal-oxide-semiconductor transistor in silicon with a channel width ( approximately 10 nanometers) smaller than the Debye screening length of a single electron and a nanoscale polysilicon dot ( approximately 7 nanometers by 7 nanometers) as the f...

Current through voltage-gated K+ channels underlies the action potential encoding the electrical signal in excitable cells. The four subunits of a voltage-gated K+ channel each have six transmembrane segments (S1-S6), whereas some other K+ channels, such as eukaryotic inward rectifier K+ channels and the prokaryotic KcsA channel, have only two transmembrane segments (M1 and M2). A voltage-gated...

Current collapse effects in an Al0.25Ga0.75N/GaN HFET have been investigated under pulsed bias conditions, and a detailed investigation of current responses to changes in drain or gate bias voltage (drain-lag and gate-lag, respectively) has been performed. Three components of transient current response to changes in drain and gate bias voltages are distinguished. Surface treatment using KOH etc...

Large conductance Ca2+-activated K+ channels (BK channels) gate open in response to both membrane voltage and intracellular Ca2+ The channel is formed by a central pore-gate domain (PGD), which spans the membrane, plus transmembrane voltage sensors and a cytoplasmic gating ring that acts as a Ca2+ sensor. How these voltage and Ca2+ sensors influence the common activation gate, and interact with...

A new output structure for class E power amplifier (PA) is proposed in this paper. A series LC resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. This resonator causes low impedance at the second harmonic. The output circuit is designed to shape the switch voltage of the class E amplifier and lower the voltage stress of the transistor. T...