Vehicular communications have received a lot of attention in recent years due to the demand for applications to improve safety and travel comfort. Nowadays, IEEE 802.11p seems to be the best positioned standard for providing safety services. However, for non-safety services, which usually do not present tight time restrictions but require high data transfer rates, other wireless communication s...

In the development and commercialization phase of information technology products implemented as a system on a chip (SoC), field-programmable gate array (FPGA) based platform has been widely used as the logic function test methodology for basic or advanced features and mobile station emulator. In this situation, to define the uniform verification approach on FPGA development platform, we introd...

In this paper, a novel evolutionary algorithm for intrinsic hardware evolution of Field Programmable Gate Array (FPGA) controllers is presented. The main feature of the evolutionary algorithm consists of a mutation operator, in which the mutation rate is defined according to the fitness. Experimental results on a Kephera robot show that the algorithm proposed can successfully navigate the robot...

This paper describes the design and evaluation of the PCA (Plastic Cell Architecture) cell, which implements a novel space allocation method. PCA is a dynamically reconfigurable architecture which exceeds the FPGA (Field Programmable Gate Array) in flexibility and generality. Circuit dynamically reconfiguration is achieved as administrators manage the heap areas. But, because objects operate an...

In this paper we discuss the development of two emulation platforms for transactional memory systems on a single Field Programmable Gate Array (FPGA). We introduce two systems, integrating only off-the-shelf components, that respectively use a centralized and a distributed approach, presenting their hardware and software design. We analyze and compare these two architectures to a lock based mul...

1 A tool has been created for use in a design course to automate integration of new components into a SystemOn-Chip (SoC). Students used this tool to implement a complete SoC Internet firewall, which was prototyped and tested using a field-programmable gate array (FPGA). Common components of the framework were completed as machine problem assignments throughout the first half of the semester. D...

The implementation of 3D stereo matching in real time is an important problem for many vision applications and algorithms. The current work, extending previous results by the same authors, presents in detail an architecture which combines the methods of Absolute Differences, Census, and Belief Propagation in an integrated architecture suitable for implementation with Field Programmable Gate Arr...

The PetaFlops Router is a new approach to computing wherein network architecture and compute decisions are customized for a particular application. New FieldProgrammable Gate Array (FPGA) and router technologies including multi-gigabit transceivers and application specific blocks can provide vastly improved performance. The PetaFlops Router provides greatly improved data transfer rates, computa...

This paper presents the design decisions encountered during the development of a specialised processor for the Monte-Carlo simulation of metallurgical sintering. Several possible architectures are presented. We show that such a specialised processor using commercially available gate array technology can solve the same problem more than 100 times faster than a modern high-end workstation. Even u...

This paper describes ongoing work involving the use of the X i l i n x X C 6 2 1 6 r a p i d l y reconfigurable field-programmable gate array to evolve sorting n e t w o r k s u s i n g g e n e t i c programming. We successfully evolved a network for sorting seven items that employs two fewer steps than the sorting network described in a l962 patent and that has the same number of steps as the ...