نتایج جستجو برای: floating gate mos

تعداد نتایج: 70308  

2001
Paul Hasler Bradley A. Minch

We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its dc operating point adaptively. Because the hot-electron injection is an inherent part of the pFET’s behavior, we obtain this adaptation with no additional circuitry. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less t...

2016
Kai-Yuen Lam Jung-Sheng Huang Yong-Jie Zou Kuan-Wei Lee Yeong-Her Wang

This study presents the fabrication and improved properties of an AlGaAs/InGaAs metal-oxide-semiconductor pseudomorphic high-electron-mobility transistor (MOS-PHEMT) using liquid phase deposited titanium dioxide (LPD-TiO₂) as a gate dielectric. Sulfur pretreatment and postoxidation rapid thermal annealing (RTA) were consecutively employed before and after the gate dielectric was deposited to fi...

2002
Robert W. Dutton Chang-Hoon Choi

Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leaky MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on quantum-mechanical models, and shown to be an issue of growing concern.

Journal: :Nanoscale 2013
Sung-Wook Min Hee Sung Lee Hyoung Joon Choi Min Kyu Park Taewook Nam Hyungjun Kim Sunmin Ryu Seongil Im

We report on the nanosheet-thickness effects on the performance of top-gate MoS(2) field-effect transistors (FETs), which is directly related to the MoS(2) dielectric constant. Our top-gate nanosheet FETs with 40 nm thin Al(2)O(3) displayed at least an order of magnitude higher mobility than those of bottom-gate nanosheet FETs with 285 nm thick SiO(2), benefiting from the dielectric screening b...

Journal: :IEEE Transactions on Electron Devices 2023

We present a charge-based Verilog-A model for 2-D-material (2DM)-based field-effect transistors (FETs) with application in neuromorphic circuit design. The combines the explicit solution of drift-diffusion transport and electrostatics, including Fermi–Dirac statistics. Ward–Dutton linear charge partitioning scheme is then employed terminal charges capacitance calculations. accurately predicts e...

2003
M. M. A. Hakim A. Haque

We propose a computationally efficient, accurate and numerically stable quantum-mechanical technique to calculate the direct tunneling ~DT! gate current in metal-oxide-semiconductor ~MOS! structures. Knowledge of the imaginary part G of the complex eigenenergy of the quasi-bound inversion layer states is required to estimate the lifetimes of these states. Exploiting the numerically obtained exp...

2004
Jean-Pierre Colinge Jong-Tae Park

−The EKV model, a continuous model for the MOS transistor, has been adapted to both partially depleted SOI MOSFETs with grounded body (GBSOI) and dynamic threshold MOS (DTMOS) transistors. Adaptation is straightforward and helps to understand the physics of the DTMOS. Excellent agreement is found between the model and the measured characteristics of GBSOI and DTMOS devices Index Terms− Silicon-...

2004
BOGDAN MAJKUSIAK

A theoretical description of gate tunnel current in an MOS transistor is proposed, and the results of calculations for the case of an n-channel MOSFET with extremely thin gate oxides are given. A comparison of the gate tunnel current with the drain current is made.

2003
M. W. Dashiell A. T. Kalambur R. Leeson K. J. Roe J. F. Rabolt J. Kolodzey

The gate conductor material affects the threshold voltage of metal-oxidesemiconductor (MOS) transistors through the influence of the electrochemical work function and electric charge. Measurements of the threshold voltage from current voltage characteristics may therefore provide a method to estimate the electronic properties of biomolecules located on the gate electrode. We have deposited DNA ...

2007
Androula G. Nassiopoulou S. Argyropoulos

MN178 Electrical characterization of InAs-nanocrystal-based nonvolatile memories Moïra Hocevar, Philippe Regreny, Michel Gendry, Abdelkader Souifi Institut des Nanotechnologies de Lyon-INL, UMR-CNRS-5270, INSA de Lyon, 7 avenue Jean Capelle, 69621 Villeurbanne Cedex, France, [email protected] The development of highly integrated nonvolatile memory (NVM) devices has led to the use of Si...

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