The design methods and optimization of the 32nm CMOS EIS (Efficient Inverter scheme) comparator circuit for an N bit flash A/D converter are presented in this paper. Flash A/D converter requires 2 n -1 comparators. Each one different from all others depends on the particular design. The used analog power supply in this comparator is only 1V. Low voltage analog design is necessary to compile so ...

Ongoing advances in semiconductor technology have enabled a multitude of portable, low power devices like cellular phones and wireless sensors. Most recently, as transistor device geometries reach the nanometer scale, transistor characteristics have changed so dramatically that many traditional circuits and architectures are no longer optimal and/or feasible. As a solution, much research has fo...

A 0.88 mm2 65-nm analog-to-digital converter (ADC)-based serial link transceiver is designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The MLSD is optimized in a pipelined look-ahead architecture to reach 10 Gb/s at 5.8 pJ/b and 5 Gb/s at 3.9 pJ/b, making it practical for an energy-efficient ADC-based serial link. Compared with linear equalizer and decision fee...

A development of an intelligent traffic signal control (ITSC) system needed because present traffic light controllers are based on old microcontroller such as AT89C51 which has very less internal memory and no in-built ADC. These systems have limitation because they will use the predefined program that does not have the flexibility of modification on real time application. The present traffic s...

We have proposed a flash analog-to-digital converter (ADC) that uses resonant-tunneling complex gates not only as ternary quantizers but also as ternary-to-binary encoder circuits. The ternary quantizers, consisting of monostable-to-multistable transition logic (MML) circuits, convert the analog input signal into the ternary thermometer code. This code is then converted into the binary Gray-cod...

We have estimated the performance of a flash analog-to-digital converter (ADC) that consists of ternary quantizers and a ternary-to-binary encoder using resonant-tunneling diodes (RTDs). The ternary quantizers consist of resonant-tunneling monostable-to-multistable transition logic (MML) circuits, while the encorder consists of multiple-valued multiple -input monostable-to-bistable transition l...

iii Acknowledgements I would like to thank the following people for their contributions to this work. a constant source of support throughout my time at Carnegie Mellon. This work would not have been possible without him. He was responsible for much of the digital circuit design and layout for the test chips and gathered the statistical data from the first comparator test chips.

The digital processing signal is one of the subdivisions of the analog digital converter interface; data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of lo...

The energy efficiency of ADCs has improved by orders of magnitude over the past two decades. Even though process scaling degrades the analog characteristics of transistors, by exploiting, scaling the energy efficiency of recently reported ADCs is approaching fundamental limits [1]. These improvements have been achieved through innovative circuit ideas and through the evolution of ADC architectu...