In today’s ASIC market validating a VLSI design in a field programmable gate array (FPGA) device before tape out can save a significant amount of time and therefore, money up front in the design process. At the University of California, Davis, we are working on the design of a highly parallel, reconfigurable processor chip, known as the Asynchronous Array of simple Processors (AsAP). This repor...

This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems. More over UAV autopilot has to deal with extremely adverse situations in the shortest possible time, while accomplishing its mission. FPGAs in t...

This paper introduces a new field programmable gate array (FPGA) based stochastic low-density parity-check (LDPC) decoding process, to implement fully parallel LDPCdecoders. The proposed technique is designed to optimize the FPGA logic utilisation and to decrease the decoding latency. In order to reduce the complexity, the variable node (VN) output saturated-counter is removed and each VN inter...

The paper deals with the problem of designing main FPGA-cell blocks with the current-mode gates – novel digital gates operating with constant, continuous power supply current. Using proposed approaches to designing digital current-mode circuits, the current-mode prototypes of several digital circuits and the Spartan II slice are designed. The obtained circuits are characterized by smaller hardw...

This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit and describes how this problem can be formalized and solved using Quantified Boolean Satisfiability. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has ...

On-chip Built-In Self-Test (BIST) based diagnosis of the embedded Field Programmable Gate Array (FPGA) core in a generic System-on-Chip (SoC) is presented. In this approach, the embedded processor core in the SoC is used for reconfiguration of the FPGA core for BIST, initiating the BIST sequence, retrieving the BIST results, and for performing diagnosis of faulty programmable logic blocks, memo...

Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. In this paper, we present a field-programmable gate array impleme...

Many optimization problems have complex search space, which either increase the solving problem time or finish searching without obtaining the best solution. Genetic Algorithm (GA) is an optimization technique used in solving many practical problems in science, engineering, and business domains. Parallel Genetic Algorithm (PGA) has been widely used to increase speed of GA, especially after the ...

Field programmable gate array (FPGA) devices typically have limited resources. This means that networks of FPGAs are required for implementing large-scale applications. Use of realtime communication channels can be used for reducing handshaking overhead in order to create high-performance networks. This paper describes a switched, real-time, link-level protocol and its implementation using Virt...