نتایج جستجو برای: dsp processor

تعداد نتایج: 48637  

2005
Akhmad Mulyanto Dani Fitriyanto Tati L. R. Mengko Armein Z. R. Langi

A DSP engine for discrete wavelet transformation (DWT) is introduced in this paper. Serial processing DWT architecture provides a better speed and efficiency, makes DWT better choice for image processing than DCT. A dedicated hardware DWT architecture attached to a general purpose microprocessor provided the programmability of data access make possible for dynamic scheduling for various DSP app...

Journal: :International Journal of Research in Engineering and Technology 2013

2000
Dmitri Fontine Vladimir Tchernikov Pavel Vixne Pavel Chevtchenko

The paper describes the architecture of the NeuroMatrix® NM6403 DSP designed for image processing, signal processing and neural networks emulation [1,2]. The paper includes a brief description of the processor structure and its instruction set. The NM6403 is the first DSP based on NeuroMatrix® Core (NMC) comprises an original 32-bit VLIW RISC processor and a 64-bit SIMD Vector co-processor (VCP...

Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to...

Journal: :IEEE Transactions on Industrial Electronics 2021

Capacitance monitoring is one of the important issues for a modular multilevel converter (MMC) to obtain high reliability. Since pulsewidth modulation usually implemented in field-programmable gate array (FPGA), produced precise switching states FPGA cannot be directly accessed by top digital signal processor (DSP) controller, which poses challenges existing capacitance methods based on MMC. Th...

Journal: :J. Inf. Sci. Eng. 2012
Shiao-Li Tsao Sung-Yuan Lee

Embedded systems often use a heterogeneous multi-core processor to improve performance and energy efficiency. This multi-core processor is composed of a general purpose processor (GPP), which manages the program flow and I/O, and a digital signal processor (DSP), which processes mass data. An inter-processor communication (IPC) mechanism is thus required to exchange data between a GPP and a DSP...

Journal: :Journal of physics 2023

Abstract This study presents a comprehensive simulation of digital control applications for grid-connected photovoltaic (GCPV) system using Hardware-in-the-Loop (HIL) approach that incorporates Digital Signal Processor (DSP). The is carried out the MATLAB Simulink block set and employs frequency domain controller as algorithm. inputs, which consist voltage current sensor readings, are processed...

Journal: :Energies 2021

In this study, an adaptive driving method for synchronous rectification in bidirectional full-bridge LLC resonant converters used railway applications is proposed. The drain to source voltage of the rectifier utilized detect conduction body diode, and a suitable signal generated accordingly. proposed scheme simple can be realized using low-cost digital processor (DSP). According experimental re...

2002
A. Abbas A. Ahmed Waheed Uz Zaman Bajwa A. Anwar S. Abbasi

This paper presents BURAQ, a DSP development framework, which aims at optimizing cost, efficiency and turn around time of System-On-Chip development. BURAQ accepts an Instruction and Architecture description (IAD) file that represents the DSP and its instruction set at a higher level of abstraction, in a proprietary language. The system then synthesizes a complete hardware description of the pr...

2012
Koji Kugata Shinpei Soda Yohei Nakata Shunsuke Okumura Shintaro Izumi Masahiko Yoshimoto Hiroshi Kawaguchi

We propose novel multicore architecture in which dual processors (positive-true processor element and negativetrue processor element: pPE and nPE) can be combined and serve as a low-voltage/high-performance single PE. The coupling processor occupies a double area, but it operates at a lower voltage or faster than the original processor. The proposed scheme is suitable to voltage scaling on mult...

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