Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneous 3D-ICs. TSV-induced channel length directional ( $S_{ZZ}$ ) predominantly causes variations of on-state current $\Delta I_{on}$ ). NSFETs exhibit...

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increase...

In this paper we report a study on the small signal characterization and simulation of Single Halo (SH) thin film Silicon-on-Insulators (SOI) nMOSFETs for analog and mixed signal applications. The single halo structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent DC output characteristics...

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output c...

This paper describes integration of an advanced composite high-K gate stack (4nm TaSiOx-2nm InP) in the In0.7Ga0.3As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (tOXE) and low gate leakage (JG) and (ii) effective carrier confinement and high effective carrier velocity (Veff) in the QW channel...

This paper analyzes in detail the Fringing Induced Barrier Lowering (FIBL) in MOS transistors with high-K gate dielectrics using two-dimensional device simulations. We found that the device short channel performance is degraded with increase in gate dielectric permittivity(Kgate) due to an increase in the dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we obse...

A novel structure of double-gate (DG) NMOSFET, which is formed by a strained silicon (Si) channel by using Si/Si1−xGex/Si, is proposed for the improvement of device characteristics. For analyzing the nano-scale DG MOSFET, a two-dimensional quantum-mechanical (QM) approach for solving the coupled Poisson-Schrödinger equations is reported. The advantages of a strained Si channel of DG MOSFET are ...

In this paper we describe the tunneling junction model effect on silicon nanowire gate-allaround field effect transistor using CMOS 45 nm technology. Tunneling effects provides better subthreshold slope, excellent drain induced barrier lowering and superior ION-IOFF ratio.This paper demonstrates the gate controlled tunneling at source of Gate-all-around field effect transistor. Low leakage curr...