In this work, we investigate the spin and valley transport properties of a $\mathrm{W}{\mathrm{Se}}_{2}$ monolayer placed on top ferromagnetic insulator. We are interested in controlling by applying external potentials to system. To obtain polarizations, consider single- double-barrier structure with gate potentials. analyze how efficiency these polarized depends gate-potential intensities geom...

To manage the increasing static leakage in low power applications and reduced Ion/Ioff due to aggressive scaling of MOS transistors, Tunnel FET (TFET) devices are considered as the most promising candidates because of their excellent immunity against such important short channel effects. Solutions for leakage reduction as well as improving on current of the device are sought at the device desig...

A modeling approach to study advanced floating body Z-RAM memory cells is developed. In particular, the scalability of the cells is investigated. First, a Z-RAM cell based on a 50 nm gate length double-gate structure corresponding to state of the art technology is studied. A bi-stable behavior essential for Z-RAM operation is observed even in fully depleted structures. It is demonstrated that b...

In this work we fabricate and characterize field-effect transistors based on the solution-processable semiconducting polymer poly(3-hexylthiophene) (P3HT). Applying two independent gate potentials to the electrolyte-gated organic field-effect transistor (EGOFET), by using a conventional SiO(2) layer as the back-gate dielectric and the electrolyte-gate as the top-gate, allows the measurement of ...

The rapid scaling of integrated circuit requires further shrinkage of lateral device dimension, which correlates with pillar thickness in vertical structure. This paper investigates the effect of pillar thickness variation on vertical double gate MOSFET (VDGM) fabricated using oblique rotating ion implantation (ORI) method. For this purpose, several scenarios of silicon pillar thickness tsi wer...

Articles you may be interested in Possible unified model for the Hooge parameter in inversion-layer-channel metal-oxide-semiconductor field-effect transistors J. Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor GaN metal-oxide-semiconductor field-effect transistor inversion channel mobility modeling Modeling ...

Advanced f oating body Z-RAM memory cells are studied and in particular, their scalability is investigated. First, a Z-RAM cell based on a 50nm gate length double-gate structure corresponding to state of the art technology is studied. A bi-stable behavior essential for Z-RAM operation is observed even in fully depleted structures. It is demonstrated that by adjusting the supply source-drain and...

This study proposed a novel 4H-SiC double trench metal-oxide-semiconductor field-effect-transistor (DTMCD-MOSFET) structure with built-in MOS channel diode. Further, its characteristics were analyzed using TCAD simulation. The DTMCD-MOSFET comprised active and dummy gates that divided horizontally; the diode operated through gate p-base N+ source regions at bottom of gate. Because bult-in was p...

The influence of different gate-layout geometries on a cascode nMOSFET’s transit frequencywas studied. Four cascode nMOSFET transistors were fabricated using different interdigitized gate layout geometries. Furthermore, a conventional cascode transistor was fabricated in order to compare it with the proposed interdigitized layouts. The transistors were measured on-wafer and the maximum transit ...

Circuit design of 2-input reconfigurable dynamic logic based on double gate MOSFETs with the whole set of 16 functions has been newly described. 16 function 12T DRDLC with two states (+V, 0) of control gate voltages and 14T DRDLC with two states (0, -V) of control gate voltages have been newly proposed. From these two states control gate case, 12T DRDLC with three states (+V, 0, -V) of control ...