Verifiable computation in zero knowledge allows the verifier to prove that he performed the computation of a certain functionality correctly without having to repeat the entire computational process, and without revealing any details of the computation. Any program can be represented by a circuit, and verifying the correctness of the computation is equivalent to checking circuit satisfiability ...

Powerful skew arithmetic circuits are introduced. These are skew arithmetic circuits with variables, where input gates can be labelled with powers xn for binary encoded numbers n. It is shown that polynomial identity testing for powerful skew arithmetic circuits belongs to coRNC, which generalizes a corresponding result for (standard) skew circuits. Two applications of this result are presented...

In this paper, a generic algorithm designed for the parallel evaluation of arithmetic circuits is given. This algorithm can be used in the domain of VLSI design, in order to get tight upper bounds on the computing time of a circuit. It can also be used in automatic parallelization of numerical programs, as a guide for the detection of some predeenite schemes such as dot-products or reductions. ...

Linearization and planarization of the circuit models is pivotal to the submicron technologies. On the other hand, the characteristics of the VLSI circuits can be sometimes improved by using the multivalued components. It was shown that any `-level circuit based on the multivalued components is representable as an algebraic model based on ` linear arithmetic polynomials mapped correspondingly i...

Galois field arithmetic is a critical component in communication and security-related hardware, requiring dedicated arithmetic circuit architectures for greater performance. In many Galois field applications, such as cryptography, the datapath size in the circuits can be very large. Formal verification of such circuits is beyond the capabilities of contemporary verification techniques. This pap...

In the uniform circuit model of computation, the width of a boolean circuit exactly characterises the “space” complexity of the computed function. Looking for a similar relationship in Valiant’s algebraic model of computation, we propose width of an arithmetic circuit as a possible measure of space. We introduce the class VL as an algebraic variant of deterministic log-space L. In the uniform s...

Emerging devices promise energy-efficient computing on a massively parallel scale, but due to the extremely high integration density the previously insignificant dissipation due to information erasure (destruction) becomes a prominent circuit design factor. The amount of heat generated by erasure depends on the degree of logical reversibility of the circuits and successful adiabatic charging. I...

In many problems, such as the analysis of electrical circuits, one has to deal with Differential-Algebraic Equations (DAE’s). Knowing their generic index is of interest for practical and numerical as well as for theoretical reasons. In this paper we give an algorithm that determines the generic index of the Circuit Equations of linear active electrical networks in polynomial time from tlie netw...

Contrary to indications made by prior researchers, digital logic circuits designed by artificial evolution to perform binary arithmetic tasks can generalise on inputs which were not seen during evolution. This phenomenon is demonstrated experimentally and speculatively explained in terms of the regular structure of binary arithmetic tasks and the nonoptimality of random circuits. This explanati...

An arithmetic circuit is just like a boolean circuit, except that the gates are either multiplication or addition gates, and the inputs are either variables or constants. Formally, it is a directed acyclic graph where every vertex has in-degree (aka fan-in) 2 or 0, each vertex (aka gate) of in-degree 0 is labeled by a variable or a field element, and every other vertex is labeled either + or ×....