This paper presents a VLSI circuit implementation for both the short-term memory (STM) and long-term memory (LTM) of the adaptive resonance theory neural network (ART1-NN). The circuit is implemented based on the transconductance-mode approach and mixed analog/digital components, in which analog circuits are used to fully incorporate the parallel mechanism of the neural network, whereas digital...

This paper presents web-based virtual laboratory system for electronic and digital circuit experiments. Through our virtual laboratory, the learners will be capable of learning the concepts and theories related to circuit experiments and how to operate the virtual experimental equipments such as multimeters, function generators, digital oscilloscopes, DC power suppliers and bread board etc. The...

Digital adders form a significant part of the arithmetic unit in the processors. Many Digital Signal Processing (DSP) algorithms equally uses adder and multiplier element as its component to achieve the required arithmetic operation. Hence it is important to optimize the adder circuit in the gate-level itself to design it for the required standards. Recently there are various bio-inspired optim...

A Sigma-delta modulator is designed in 180nm CMOS process for digital Audio applications. This design is simulated on S-Edit of Tanner EDA tool. In this design continuous time sigma-delta modulator is implemented to reduce the noise problem. This sigma-delta modulator also helps to reduce power consumption of circuit. In these design two stage op-amps is used to implement modulator. Also this d...

This work presents a novel noise-shaping cascaded sigma-delta modulator that incorporates two stages. The first stage is realized by low-order single bit architecture, while the second stage is realized by a high-order feed-forward multi-bit architecture. Moreover, the error cancellation schemes can be added in the digital circuit part to cancel the coarse quantization errors and thus effective...

A very low power mixed-signal design methodology based on subthreshold sourcecoupled circuits is presented, and a nano-Watt range analog-to-digital converter (ADC) circuit based on folding-interpolating topology is proposed as a complete design example. To reduce the power dissipation to sub-μW level, subthreshold source-coupled circuit family has been developed for both analog and digital part...

This paper proposes and analyses the performance of a Genetic Algorithm using two new concepts, namely a static fitness function including a discontinuity measure and a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. In both cases, experiments reveal superior results in terms of speed and convergence to achieve a solution.

A simple circuit for measuring both polar and Cartesian coordinates of an impedance is proposed.

The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap quantum well channels inside the substrate of the semiconductor. Applied voltage at the gate region of the SWSFET, switches the charge carrier concentration in different channels from source to drain region. The switching of electron wave function in different channels can be explained by the devic...

Verification of analog circuit specifications is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost parameter verification based on statistical analysis of a digital signature. A CMOS on-chip monitor and sampler circuit generates the digital signature of the CUT. The monitor composes two signals (x(t), y(t)) and divides...