نتایج جستجو برای: design new adder
تعداد نتایج: 2645988 فیلتر نتایج به سال:
Single-Electron-Technology (SET) is one of the future technologies distinguished by its small and low power devices. SET also provides simple and elegant solutions for threshold logic gates (TLG’s). This paper presents the design of an optimal TLG adder implemented in SET. It provides a detailed procedure for designing capacitive– input SET TLG’s for building the adder. The paper also presents ...
Quantum computers require quantum processors. An important part of the processor of any computer is the arithmetic unit, which performs binary addition, subtraction, division and multiplication, however multiplication can be performed using repeated addition, while division can be performed using repeated subtraction. In this paper we present two designs using the reversible R gate to perform t...
Full adders are essentially used as a building block in all arithmetic, DSP and microprocessor applications. In this paper, a 15 transistor hybrid PTL-TG full adder circuit is proposed. The main objective is to provide high speed, low power, full swing operation with good drivability. The choice of logic design affects the circuit performance. The delay time depends on the number of transistors...
In this paper, we proposed a low power 1-bit full adder (FA) with 10-transistors and this is used in the design ALU. 16-bit ALUs are designed and compared with the existing design. The proposed design consists of PTL-GDI adder and mux circuits. By using low power 1-bit full adder in the implementation of ALU, the power and area are greatly reduced to more than 50% compared to conventional desig...
--------------------------------------------------------------ABSTRACT------------------------------------------------------Ultra-high energy efficiency is required for all the battery operated devices due to increased functionality on the single chip. In conventional digital VLSI design, it is assumed that a circuit/system should function perfectly to provide accurate results.There are many ap...
In this paper, we designed and simulated a low power one bit, 8-bit and 32-bit full adder circuits namely Novel 10T, N14T, FA24T, CPL (complementary pass-transistor logic) and DPL (double pass-transistor logic). All the adders are tested by using one bit, 8-bit and 32-bit ripple carry adder architecture using Tanner EDA tool version 13. 0. The one bit Novel 10T, N14T, XOR/XNOR function techniqu...
Quantum-dot cellular automata (QCA) are an emerging technology and a possible alternative for faster speed, smaller size, and low power consumption than semiconductor transistor based technologies. Previously, adder designs based on conventional designs were examined for implementation with QCA technology. This paper utilizes the QCA characteristics to design a fault-tolerant adder that is more...
Programmable reversible logic circuit is design style for nanotechnology and quantum computing with minimum heat generation, quantum cost and garbage output. Late advances in reversible rationale utilizing and quantum PC calculations consider enhanced PC engineering and math rationale unit plans. In this paper, we survey the N-bit reversible logic adder and sub tractors are used with minimal de...
This paper presents the design for low power circuilts which use reversible logic to conserve energy. The project presents the implementation of a Sklansky tree adder structure using a quasi static adiabatic logic namely CEPAL (Complementary Energy Path Adiabatic Logic). The SKLANSKY Tree adder structure has been chosen due to its increased fan-out that results in reduced latency and improved s...
A new proposal is given to design a spin half-adder in nano-junction. It well known that at finite voltage net circulating current (known as circular current) appears within mesoscopic ring under asymmetric ring-to-electrode interface configuration. This induces magnetic field the center of ring. We utilize this phenomenon construct half adder. The induced used regulate alignments local free sp...
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