Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, we proposed a design space exploration framework using analytical modeling. We have considered many-many mapping between cores and switches. A buffer allocation algorithm for wormhole routing based networks-on-chip is proposed for the design space exploration. When the total budget of t...

Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based...

We propose two kinds of wire configurations fabricated on an atom chip surface for creating two-dimensional (2D) adiabatic rf guide with an inhomogeneous rf magnetic field and a homogenous dc magnetic field. The guiding state can be selected by changing the detuning between the frequency of rf magnetic field and the resonance frequency of two Zeeman sublevels. We also discuss the optimization o...

This paper contains an in-depth study of a particular problem in order to evaluate several approaches to the solving of discrete combinatorial problems. We take a warehouse location problem as a case study and present solutions to it by using Integer Programming, a specialized program based on A* and the constraint logic programming CHIP. The merits of each approach are discussed and compared i...

testability standard in the industry. Although its mandatory provisions focus narrowly on boardlevel assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard...

We have established a certification system for antibodies to be used in chromatin immunoprecipitation assays coupled to massive parallel sequencing (ChIP-seq). This certification comprises a standardized ChIP procedure and the attribution of a numerical quality control indicator (QCi) to biological replicate experiments. The QCi computation is based on a universally applicable quality assessmen...

The paper describes the need for early analysis tools to enable developers of today’s system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs an...

We investigate and improve the scalability of multi-core LTL model checking. Our algorithm, based on parallel DFS-like SCC decomposition, is able to efficiently decompose large SCCs on-the-fly, which is a difficult problem to solve in parallel. To validate the algorithm we performed experiments on a 64-core machine. We used an extensive set of well-known benchmark collections obtained from the ...

The aim of this study is experimental assay of sensitivity and stability of a bimetallic silver/gold SPR sensor chip. This chip utilizes the sensitivity of the silver and the stability of the gold. Moreover, the Silver layer (instead of usual Cr or Ti layer) was used as an adhesive intermediate layer between the Gold layer and the glass substrate. The optimization of the Gold/Silver thickness u...