This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 μm standard CMOS technology and the experimental results agree well with the theory. key words: time a...

A high-speed DDR2, DDR2/3, or DDR3 DRAM interface for off-chip memory provides a powerful tool to meet the high-performance demands of new electronic products. However, with advancements come new challenges. The DDR DRAM high-speed interface between the system-on-chip (SoC) and off-chip memory requires specialty circuits. These circuits, often referred to as a physical layer (PHY), comprise hig...

this paper proposes a new method for parameter estimation of distorted single phase signals, through an improved demodulation-based phase tracking incorporated with a frequency adaptation mechanism. the simulation results demonstrate the superiority of the proposed method compared to the conventional sogi (second-order generalized integrator)-based approach, in spite of the dc-offset and harmon...

In a previous work we proposed a phase-lock structure called the time-delay digital tanlock loop (TDTL). This digital phase-locked loop (DPLL) performs nonuniform sampling and utilizes a constant time-delay unit instead of the constant 90-degrees phase-shifter used in conventional tanlock structures. The TDTL reduces the complexity of implementation and avoids many of the practical problems ass...

This paper focuses on low cost production testing of the far-out phase noise of PLL ICs using the delay line discriminator method. It describes two different delay line discriminator (DLD) implementations for phase noise measurements at large frequency offsets from the carrier. The calibration method using an FM calibration signal is described in detail, both mathematically and graphically. The...

In this work classical and modern control theory methods are applied for rigorous mathematical analysis and design of different computer architecture circuits such as clock generators, synchronization systems and others. The present work is devoted to the questions of analysis and synthesis of feedback systems, in which there are controllable delay lines. In the work it is mathematically strict...