&AS TECHNOLOGY SCALES to 22 nm and functional density continues to rise, many factors and parameters have a direct impact on the design and test of chips. Among such challenges, IR-drop and power supply noise (PSN) effects have become more significant in recent years. Design and test engineers need to efficiently handle these effects because they can cause design, test, and reliability issues f...

Progress in technological scaling allows the integration into a single chip of hundreds of millions of transistors, moving quickly to the multi-billion transistor capacities. The integration of complex systems into a single chip, that may include heterogeneous parts such as logic, SRAM, DRAM non-volatile memories, analog and even micromechanical and optical parts, is becoming a reality. Achievi...

Dual-metal gate CMOS devices with rapid-thermal chemicalvapor deposited (RTCVD) Si3N4 gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and MO for the Nand PMOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for Si02. C-V characteristics show good agreement with a simulation that takes quantum-mechanica...

Diagnosis of malfunctioning deep-submicron (DSM) ICs is becoming more dificult due to the increasing sophistication of the manufacturing process and the structural complexity of the IC itself: At the same time, key diagnostic tusks that include defect localization are still solved using primitive models of the IC’s defects. This paper explores the use of “jault tuples” in diagnosis. Fault tuple...

This paper describes the requirements that quiescent current (IDDQ) testing must meet in order to continue being useful in the face of rising background currents. Using projections from the 1999 International Technology Roadmap for Semiconductors, several different techniques are evaluated to determine their usefulness in future technologies.

Cursa continuă pentru reducerea dimensiunilor fizice în circuitele integrate este limitată în prezent de considerente fizice, tehnologice şi economice. Subiectul acestei lucrări este trecerea în revistă în primele două secţiuni a unora dintre problemele apărute datorită reducerii dimensiunilor tranzistoarelor şi a prelucrării tehnologice, precum şi a principalelor probleme întâlnite în proiecta...

The resistance of on-chip interconnects and the current drive of transistors is strongly temperature dependent. As a result, the interconnect performance is affected by the temperature in a sizeable proportion. In this paper we evaluate thermal effects in global RLC interconnects and quantify their impact in a standard optimization procedure in which repeaters are used. By evaluating the differ...

Title of dissertation: DEEP SUBMICRON CMOS VLSI CIRCUIT RELIABILITY MODELING, SIMULATION AND DESIGN Xiaojun Li, Doctor of Philosophy, 2005 Dissertation directed by: Professor Joseph B. Bernstein Reliability Engineering CMOS VLSI circuit reliability modeling and simulation have attracted intense research interest in the last two decades, and as a result almost all IC Design For Reliability (DFR)...

0740-7475/02/$17.00 © 2002 IEEE July–August 2002 EDA FLOWS are industry driven, and thus use synchronous methodologies as de facto standards. However, implementation problems arise from imposing a synchronous model of operation on deep-submicron circuits. This problem motivates the investigation of other, asynchronous modes of operation. Acceptance of new design methodologies, including asynchr...