This proposal deals with the design of scheduling algorithms for Combined Input and Output Queued (CIOQ) switches. For crossbar based switches, we demonstrate the poor performance of commonly used scheduling algorithms under overload traffic conditions using targeted stress tests and present ideas to develop robust, stress resistant versions of these algorithms which are still simple enough to ...

This paper presents a theoretical throughput analysis of two buffered-crossbar switches, called shared-memory crosspoint buffered (SMCB) switches, in which crosspoint buffers are shared by two or more inputs. In one of the switches, the sharedcrosspoint buffers are dynamically partitioned and assigned to the sharing inputs, and memory is sped up. In the other switch, inputs are arbitrated to de...

Input buffered switches have the strong advantage of efficient crossbar usage. Virtual Output Queueing (VOQ) has to be established to circumvent the head-of-line (HOL) blocking which limits the throughput to 58.6%. Arbitration algorithms control the access to the switch fabric in each time slot. Weighted algorithms achieve 100% throughput with lowest delays under all admissible traffic even und...

Extremely dense neuromorphic networks may be based on hybrid 2D arrays of nanoscale components, including molecular latching switches working as adaptive synapses, nanowires as axons and dendrites, and nano-CMOS circuits serving as neural cell bodies. Possible architectures include ‘free-growing’ networks that may form topologies very close to those of cerebral cortex, and several species of di...

Multistage interconnection networks are frequently proposed as connections in multiprocessor systems or network switches. In this paper, a new tool for stochastic simulation of such networks is presented. Simple crossbars can be simulated as well as multistage interconnection networks that are arranged in multiple layers.

While serial transceivers move data in and out of an ASIC, on-chip global interconnects move data inside the ASIC. These global interconnects include crossbar switches and busses for sharing on-chip resources. To guarantee quality of service, the on-chip global interconnects are often designed to carry several times worth of traffic compared to the serial transceivers. Close to 10 Tb/s is not a...

Switches in interconnection networks for highly parallel shared memory computer systems may be implemented with different internal buffer structures. For a 2×2 synchronous switch, previous studies have often assumed a switch composed of two queues, one at each output, each of which has unbounded size and may accept two inputs every clock cycle. Hardware implementations may actually use simpler ...

Scalability of Cluster-Computers utilizing Gigabit-Ethernet as an interconnect is limited by the unavailability of scalable switches that provide full bisectional bandwidth. Clos’ idea of connecting small crossbar-switches to a large, non-blocking crossbar – wide-spread in the field of high-performance networks – is not applicable in a straightforward manner to Ethernet fabrics. This paper pres...

A high-performance variable-length packet scheduling algorithm is proposed for efficiently accommodating IP traffic in inputqueued crossbar switches. It uses a rotating priority(round-robin) arbitration and a masking operation for variable-length packets. This algorithm achieves 100% throughput with a single iteration for uniform IP traffic and performs better packet latency and similar cell la...

Combined input-crosspoint buffered (CICB) switches relax arbitration timing and provide high-performance switching for packet switches with high-speed ports. It has been shown that these switches, with one-cell crosspoint buffer and round-robin arbitration at input and output ports, provide 100% throughput under uniform traffic. However, under admissible traffic patterns with nonuniform distrib...