We present optimal solutions to the test scheduling problem for core-based systems. Given a set of tasks (test sets for the cores), a set of test resources (e.g., test buses, BIST hardware) and a test access architecture, we determine start times for the tasks such that the total test application time is minimized. We show that the test scheduling decision problem is equivalent to the -processo...

At-speed testing of high-speed circuits is becoming increasingly difficult with external testers. Therefore, empowering the chip to test itself seems like a natural solution. Hardware-based selftesting techniques have limitations due to performance and area overhead as well as problems caused by application of non-functional patterns. Another possible solution is software-based self-testing whe...

The testing of embedded cores (or Virtual Components [VCs], as the VSI Alliance calls them) in an environment where the system-chip is composed of multiple cores from different authors, requires that the chosen test strategy and methodology allow for the identification of the failing core (VC), as well as determining that the manufactured chip is of sufficient quality to ship to a customer. Thi...

THE CURRENT TREND of SoC design has made conventional test methodologies increasingly difficult. Performing brute-force test pattern generation (ATPG) on the entire SoC is often infeasible, because the design can exceed the test pattern generator’s capabilities. At other times, some black-box third-party cores within the SoC might have their own test patterns generated at the core boundary. IEE...

OBJECTIVES To evaluate whether the core-peripheral temperature gradient could be used to distinguish between cardiac and respiratory causes of dyspnoea. METHODS In total, 50 patients were enrolled in the study, based on the following inclusion criteria: (a) a primary presenting complaint of dyspnoea; (b) age > 40 years; (c) respiratory rate > 20 breaths/min; (d) hypoxia. The tympanic temperat...

The purpose of this paper is to develop a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a \bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested because they are used to propagate test ...

The veriication methodology for a TMS320C25 compatible embedded DSP core is described. The DSP core has been implemented in synthesizable VHDL and has been cosimulated with the original DSP to verify correct behavior. Automatic test case generation together with hand-crafted code has been used as a means of providing stimuli to achieve increased RTL-simulation coverage. The cosim-ulation enviro...

The increased usage of embedded pre-designed reusable cores necessitates a core-based test strategy, in which cores are tested as separate entities. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-underdevelopment that aims at improving ease of reuse and facilitating interoperability with respect to the test of core-based system chips, especially if they contain cores from diffe...

This papcr copes with the test-pattern gcneration mid hitl cuverage determilintion in the core-based design. 'l'hc basic corc-test strategy that one has to apply In the coreliiiwd design is stated in this work. A Compuier-Aided Test (CAT) flow i s propcsscd resulting in accurate fault coverage of embedded cores. T h e CAT flow is applied tu a few cores rvilhiii tlic Philips Core Test Pilot IC p...