Rice Michael, Padilla Marc, Nelson Brent, "On FM De-modulators in Software Defined Radios Using FPGAs", Grant no. 0801876, I/UCRC Program of the National Science Foundation, Provo, Utah, October 2009 Volder Jack, "The CORDIC trigonometric computing technique", IRE Transactions on Electronic Computers, vol. 8, no. 3, September 1959, pp. 330-334 Andraka Ray, "A survey of ...

This paper presents a high-throughput fixed-point complex divider which uses four pipelined CORDIC units to transform and divide complex numbers in Polar coordinates. By persevering the macro-angle for CORDIC rotations in redundant form and developing an optimized pipelining structure, the FPGA based implementation achieves a 9× advantage on throughput over the best design reported. In addition...

We propose a novel fully-pipelined parallel CORDIC architecture (CORDIC-DXT-ME) employing the DCT PseudoPhase Techniques for Motion Estimation. Its low computational complexity, O(N2) as compared with O ( N " ) of BKlI ME; makes it fascinating in real time applications. In addition, the DCT-based nature enables us to replace all multipliers by CORDICs with simple shift-and-add operations and t ...

Neural network is being used in many real life applications like prediction, classification etc. In this paper we present an FPGA hardware efficient implementation of neural network where we have implemented a multilayer feed forward network. We have used CORDIC algorithms of HP-35 scientific calculator for this purpose. The CORDIC algorithm is an approximation technique to compute trigonometri...

In this paper we develop a CORDIC-based floating-point vectoring algorithm which reduces significantly the amount of microrotation steps as compared to the conventional algorithm. The overhead required to accomplish this is minimized by the introduction of an angle selection function which considers only a few of the total amount of bits used to represent the vector being rotated. At the same t...

Contemporary hardware implementations of artificial neural networks face the burden excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured compute both mult...

For [0,∞]-valued (monotone) measures and functions, universal integrals are introduced and investigated. For a fixed pseudomultiplication ⊗ on [0,∞] the smallest and the greatest universal integrals are given. Finally, a third construction method for obtaining universal integrals is introduced.

Recently, much research has focused on the design of biped robots with stable and smooth walking ability, identical to human beings, thus, in coming years, will accomplish rescue or exploration tasks challenging environments. To achieve this goal, one important problems is a chip for real-time calculation moving length rotation angle robot. This paper presents an efficient accurate coordinate d...

This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of polyphase COordinate Rotation DIgital Computer (CORDIC) processor and multirate filter. advantage CORDIC is process with high sample rate input data produces computational efficient noiseless baseband spectrum....

| This paper presents the architecture of Jacobium processing elements. The Jacobium is a dataaow processor aiming at high speed execution of algorithms where Cordic operations play a dominant role. To achieve high throughputs the processing elements are equiped with a deep oating point Cordic pipeline, on-chip multiport memory to buuer operands and results, and several high speed communication...