The goal of the research program that we describe is to break the emerging performance wall in microprocessor development arising from limited bandwidth and density of on-chip interconnects and chip-to-chip (processor-tomemory) electrical interfaces. Complementary metal-oxide semiconductor compatible photonic devices provide an infrastructure for deployment of a range of integrated photonic net...

Continuing demands for increased compute efficiency and communication bandwidth have led to the development of novel interconnect technologies with the potential to outperform conventional electrical interconnects. With a plurality of interconnect technologies to include electronics, photonics, plasmonics, and hybrids thereof, the simple approach of counting on-chip devices to capture performan...

As technology advances to giga-scale integration level, global interconnect resource becomes increasingly valuable in a VLSI chip. This is due to the exponential growth of the total number of interconnects/wires as the feature size of MOS transistors decreases in scaled deep submicron CMOS technologies. Interconnect length, however, has not scaled down with feature size and remains long relativ...

This work describes a novel smart three axis compliant (STAC) interconnect targeted to revolutionize chipto-chip and chip-to-board high-density three dimensional (3D) integration for ultra-thin Si dies (≤ 75 μm) at the wafer level. The STAC interconnect is a 3D-compliant interconnect which allows stacked ultra-thin chips to move or flex freely during operation with negligible stress imposed on ...

We evaluate the advantages of reconfigurable optical interconnects within massively parallel systems due to their ability to provide versatile application-dependent network configurations. Furthermore, they are being considered as alternatives to electronic interconnects within high-performance computers because of their advantages of high bandwidth, low wire density and low power requirement a...

Integration of high-speed parallel optical interconnects into printed wiring boards (PWB) is studied. The aim is a hybrid optical–electrical board including both electrical wiring and embedded polymer waveguides. Robust optical coupling between the waveguide and the emitter/detector should be achieved by the use of automated pick-and-place assembly. Different coupling schemes were analyzed by c...

In deep submicron VLSI circuits, interconnect delays dominate MOSFET gate delays. Conventional buffer insertion method reduces delays at the cost of valuable chip area. Consequently, alternative methods are essential. Current mode interconnects have lesser delay than voltage mode circuits and also consume lesser chip area. In the present work, superiority of current mode over voltage mode inter...

We present germanium microdisk optical resonators under a large biaxial tensile strain using a CMOS-compatible fabrication process. Biaxial tensile strain of ~0.7% is achieved by means of a stress concentration technique that allows the strain level to be customized by carefully selecting certain lithographic dimensions. The partial strain relaxation at the edges of a patterned germanium microd...

Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. For deep submicron technologies (DSM), on-chip inductive effects have increased due to faster clock speeds, smaller signal rise times and longer length of on-chip interconnects. All these issues raise the concern for crosstalk, propagation delay and power dissipation of overall. Therefore, ...