For the first time, we study the coverage of non-target defects for Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST implementation options that result in test sequences of different lengths. Resistive bridging faults are used as a surrogate of non-target defects. Experimental data obtained for largest ISCAS benchmarks suggests that, although DLBIST always guarantees c...

A deterministic partitioning technique for fault diagnosis in Scan-Based BIST is proposed. Properties of high quality partitions for improved fault diagnosis times are identified and low cost hardware implementations of high quality deterministic partitions are outlined. The superiority of the partitions generated by the proposed approach is confirmed through mathematical analysis. Theoretical ...

In this paper we perform a comparative analysis of the encoding efficiency of BIST schemes based on reseeding of single polynomial LFSR's as well as LFSR's with fully programmable polynomials. Full programmability gives much better encoding efficiency. For a testcube with s carebits we need only s+4 bits in contrast to s+19 bits for reseeding of single polynomials, but since it involves solving...

Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniques have changed their way from traditional DFT to modern SFT approach. In this paper, we present a novel flexible register allocation method for digital circuits, which is based on considering testability parameters a...

Fault diagnosis is important in improving the design process and the manufacturing yield of nanometer circuits. It is however a challenging problem as today’s complex defects lead to an explosion of the diagnosis solution space with the increasing number of possible fault locations and fault models. Our goal in this study consists in developing a new diagnosis method targeting almost all the na...

This paper provides a new approach for object-oriented reengineering. One of the difficulty in software testing and maintenance has been identified as caused by the convention that code and its tests are developed and described separately. This paper develops a method of built-in test (BIT) for OO reengineering. The advantage of this method is that the BITs in reengineered OO software (OOS) can...

The number of embedded cores in an FPGA has been increasing and different devices use different numbers of different types of hard IP cores. To facilitate failure analysis and reduce its turnaround time, we present an automated BIST-based methodology that exploits the existing redundant resources of an FPGA and its reconfigurabilty to efficiently locate the faulty IP block(s) in addition to pas...

With the upcoming trend towards built-in test structures and implicit testing, more and more issues of test design need to be resolved during circuit design. A basic requirement for manual as well as for automatic test generation is to assess how accurately a given test strategy will classify good and faulty circuits. Measurement error plays an important role here and must be taken into account...

We present a new technique for uniquely identifying a single failing vector in an interval of test vectors. This technique is applicable to combinational circuits and for scan-BIST in sequential circuits with multiple scan chains. The proposed method relies on the linearity properties of the MISR and on the use of two test sequences, which are both applied to the circuit under test. The second ...