In this paper an improved current comparator is using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit has short propagation delay and occupies a small chip area. All circuits have been simulated employing Tanner EDA Tool 14.1v for 90nm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, comp...

We investigate a fluid buffer which is modulated by a stochastic background process, while the momentary behavior of the background process depends on the current buffer level in a continuous way. Loosely speaking the feedback is such that the background process behaves `as a continuous-time Markov chain' with generator Q(y) at times when the buffer level is y, where the entries of Q(y) are con...

A new architecture of simple low voltage BiCMOS fourquadrant multiplier is proposed and analyzed. It operates with ±1.5V power supplies and 3Vp-p fully input signal swings. Simulation results based on AMS 0.8μm n-well BiCMOS process parameters are given to verify the theoretical analysis. The architecture of four multipliers typically have a nonlinearity error less than 1% over ±1.5V input rang...

The distortion produced by a typical solid-state Class-B power amplifier is shown to consist of eight mechanisms, all of which may coexist and whose distortion products overlap to give a complex result. Methods for isolating each mechanism for study, and minimising its contribution, are given. If the avoidable distortions are designed out, Class-B amplifiers of unusually low distortion (Below 0...

This paper presents a new CMOS buffer circuit topology for radiofrequency (RF) applications based on a fully-differential voltage-combiner circuit, capable of operating at low-voltage. The proposed circuit uses a combination of common-source (CS) and common-drain (CD) devices. The simulation results show good levels of linearity and bandwidth. To improve total harmonic distortion (THD) a source...

-A novel high and low speed output buffer circuit is proposed for Universal Serial Bus (USB) interface applications. Operation principles of this novel buffer are developed based on slew rate control and delayed turn-on technique. The mechanism for slew rate control is process variation self compensating. So, both precise rise and fall times of the output signal have been obtained for low speed...

We investigate a fluid buffer which is modulated by a stochastic background process, while the momentary behavior of the background process depends on the current buffer level in a continuous way. Loosely speaking the feedback is such that the background process behaves `as a continuous-time Markov chain' with generator Q(y) at times when the buffer level is y, where the entries of Q(y) are con...

A novel reconfigurable hybrid single electron transistor/MOSFET (SETMOS) circuit architecture, namely, reconfigurable pseudo-NMOS-like logic is proposed. Based on the hybrid SETMOS inverter/buffer circuit cell, reconfigurable pseudo-NMOS-like logics that can work normally at room temperature are constructed. This kind of reconfigurable logic can implement up to 2n sorts of functions at n inputs...